AD7835 Analog Devices, AD7835 Datasheet - Page 17

• Manufacturer Part Number: AD7835
• Description: LC2MOS Quad 14-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7835

• Resolution (bits): 14bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Par

CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 21. It is capable of driving a load of 10 kΩ in
parallel with 200 pF. G
control the power-on voltage present at V
used in conjunction with the CLR input to set V
defined voltage present at the DSG pin.
POWER-ON WITH CLR LOW, LDAC HIGH
The output stage of the AD7834/AD7835 is designed to allow
output stability during power-on. If CLR is kept low during
power-on, and power is applied to the part, G
open while G
V
and R. R is a thin-film resistor between DSG and V
output amplifier is connected as a unity gain buffer via G
the DSG voltage is applied to the buffer input via G
amplifier output is thus at the same voltage as the DSG pin. The
output stage remains configured as in Figure 22 until the
voltage at V
point, the output amplifier has enough headroom to handle
signals at its input and has also had time to settle. The internal
power-on circuitry opens G
Figure 23). As a result, the output amplifier is connected in
unity gain mode via G
to the noninverting input via G
OUT
is kept within a few hundred millivolts of DSG via G
DAC
Figure 21. Block Diagram of AD7834/AD7835 Output Stage
DAC
DD
2
, G
and V
Figure 22. Output Stage with V
G
G
3
G
G
, and G
1
1
2
2
DSG
DSG
SS
4
1
reaches approximately ±10 V. At this
and G
to G
5
are closed (see Figure 22).
3
6
and G
are transmission gates used to
G
G
G
G
6
. The DSG voltage is still applied
3
5
5
3
2
. This voltage appears at V
5
R
R
and closes G
G
G
G
G
6
6
4
4
DD
OUT
< 10 V
. G
1
, G
1
OUT
and G
4
4
, and G
and G
OUT
2
to the user-
. The
V
V
OUT
OUT
. The
2
are also
6
3
6
, and
5
(see
OUT
are
Rev. D | Page 17 of 28
.
V
but tracks the voltage present at DSG via the unity gain buffer.
POWER-ON WITH LDAC LOW, CLR HIGH
In many applications of the AD7834/AD7835,
continuously low, updating the DAC after each valid data
transfer. If LDAC is low when power is applied, G
G
output amplifier. G
connecting the amplifier as a unity gain buffer, as before. V
connected to DSG via G
DSG and V
Then, the internal power-on circuitry opens G
closes G
this point, V
LOADING THE DAC AND USING THE CLR INPUT
When
The voltage at V
put of the DAC. The output stage remains connected in this
manner until a CLR signal is applied. Then, the situation reverts
(see Figure 23). Once again, V
DSG until LDAC goes low. This reconnects the DAC output to
the unity gain buffer.
OUT
2
is open, connecting the output of the DAC to the input of the
is disconnected from the DSG pin by the opening of G
LDAC
DAC
DAC
4
and G
Figure 23. Output Stage with V
OUT
OUT
goes low, it closes G
) until V
6
Figure 24. Output Stage with
is at the same voltage as the DAC output.
. This is the situation shown in Figure 24. At
OUT
G
G
G
G
1
2
1
2
DSG
3
DSG
now follows the voltage present at the out-
and G
DD
5
and R (a thin-film resistance between
and V
5
are closed and G
G
G
G
G
OUT
5
3
5
3
SS
1
reach approximately ±10 V.
remains at the same voltage as
and opens G
DD
R
R
> 10 V and CLR Low
AD7834/AD7835
G
G
G
G
LDAC
6
4
6
4
4
Low
and G
3
LDAC
2
and G
as in Figure 24.
1
is closed and
6
V
V
are open,
OUT
OUT
is kept
5
and
OUT
5
is