AD7835 Analog Devices, AD7835 Datasheet - Page 8

• Manufacturer Part Number: AD7835
• Description: LC2MOS Quad 14-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7835

• Resolution (bits): 14bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Par

AD7834/AD7835
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. AD7834 Pin Function Descriptions
Pin No.
1
2
3
4
5, 24, 25, 26, 27
22, 6, 21, 7
8
9
10
11
12,13,14,15,16
17
18
19
20
23
28
Pin Mnemonic
V
DSG
V
V
NC
V
DGND
V
SCLK
DIN
PA0 to PA4
PAEN
FSYNC
LDAC
CLR
V
AGND
SS
REF
REF
OUT
CC
DD
(−)
(+)
1 to V
OUT
4
Description
Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%.
Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of
the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin.
Negative Reference Input. The negative reference voltage is referred to AGND.
Positive Reference Input. The positive reference voltage is referred to AGND.
No Connect.
DAC Outputs.
Digital Ground.
Logic Power Supply: 5 V ± 5%.
Clock Input. Used for writing data to the device; data is clocked into the input register on the
falling edge of SCLK.
Serial Data Input.
Package Address Inputs. These inputs are hardwired high (V
package addresses in a multipackage environment.
Package Address Enable Input. When low, this input allows normal operation of the device. When
high, the device ignores the package address, but not the channel address, in the serial data
stream and loads the serial data into the input registers. This feature is useful in a multipackage
application where it can be used to load the same data into the same channel in each package.
Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to
the device with serial data expected after the falling edge of this signal. The contents of the 24-bit
serial-to-parallel input register are transferred on the rising edge of this signal.
Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal,
determines how the analog outputs are updated. If LDAC is maintained high while new data is
being loaded into the device’s input registers, no change occurs on the analog outputs.
Subsequently, when LDAC is brought low, the contents of all four input registers are transferred
into their respective DAC latches, updating all of the analog outputs simultaneously.
Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog
outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the
signal outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low,
the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR
remains low, the LDAC signals are ignored, and the signal outputs remain switched to the
potential on the DSG pin.
Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%.
Analog Ground.
Figure 6. AD7834 PDIP and SOIC Pin Configuration
V
V
REF
V
V
DGND
REF
SCLK
OUT
OUT
DSG
PA0
PA1
PA2
V
V
DIN
NC
(–)
(+)
CC
SS
2
4
Rev. D | Page 8 of 28
10
11
12
13
14
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD7834
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
NC
NC
NC
NC
V
V
V
CLR
LDAC
FSYNC
PAEN
PA4
PA3
DD
OUT
OUT
1
3
CC
) or low (DGND) to assign dedicated