AD7804 Analog Devices, AD7804 Datasheet - Page 24

• Manufacturer Part Number: AD7804
• Description: +3.3 V to +5 V Quad/Octal 10-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7804

• Resolution (bits): 10bit
• Dac Update Rate: 667kSPS
• Dac Settling Time: 1.5µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser

AD7804/AD7805/AD7808/AD7809
APPLICATIONS
Opto-Isolated Interface for Process Control Applications
The AD7804/AD7808 has a versatile serial three-wire serial
interface making it ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD7804/AD7808 from the controller. This can easily be
achieved by using opto-isolators which will provide isolation in
excess of 3 kV. The serial loading structure of the AD7804/
AD7808 makes it ideally suited for use in opto-isolated appli-
cations. Figure 41 shows an opto-isolated interface to the
AD7804/AD7808 where SDIN, CLKIN and FSIN are driven
from optocouplers. LDAC is hardwired low to reduce the number
of interface lines and this ensures that each DAC is updated follow-
ing the sixteenth serial clock of a write cycle.
Decoding Multiple AD7808s
The FSIN pin on the AD7808s can be used in applications to
decode a number of DACs. In this application all DACs in the
system receive the same serial clock and serial data, but only the
FSIN to one of the DACs will be active at any one time allowing
access to eight channels in this thirty-two channel system. The
74HC139 is used as a 2- to 4-line decoder to address any of the
DACs in the system. To prevent timing errors from occurring
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 42 shows a
system decoding multiple AD7808s in a multichannel system.
POWER
CLKIN
DATA
FSIN
Figure 41. AD7804/AD7808 Opto-Isolated Interface
V
V
V
V
DD
DD
DD
DD
REGULATOR
10k
10k
10k
1
+5V
CLKIN
CLR
LDAC
FSIN
SDIN
DGND
AD7804/
AD7808
AV
DD
DV
AGND
REFOUT
DD
10 F
V
V
V
V
REFIN
OUT
OUT
OUT
OUT
A
B
C
D
0.1 F
1 TO 10nF
–24–
AD7805 As a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using two
DACs in the AD7805 is shown in Figure 43. The upper and
lower limits for the test are loaded to DACs A and B that in
turn set the limits on the CMP04. If a signal at the V
not within the programmed window an LED will indicate the
fail condition. Only one limit detector is shown below but can
easily be adapted for a dual channel system by using the extra
DACs on the AD7805 and the two unused comparators on the
CMP04.
Figure 42. Decoding Multiple AD7808s Using the FSIN Pin
+5V
0.01 F
0.01 F
Figure 43. Digitally Programmable Window Detector
DV
DD
ADDRESS
ENABLE
CODED
CLKIN
SDIN
COMP
D9
D0
MODE
CS
WR
CLR
LDAC
0.1 F
DGND
1G
1A
1B
AV
AD7805
DD
74HC139
DGND
V
V
CC
DD
DV
AGND
DD
V
V
V
V
1Y0
1Y1
1Y2
1Y3
10 F
OUT
OUT
OUT
OUT
A
B
C
D
V
IN
CMP04
1/2
FSIN
SDIN
CLKIN
FSIN
SDIN
CLKIN
FSIN
SDIN
CLKIN
FSIN
SDIN
CLKIN
AD7808
AD7808
AD7808
AD7808
74HC05
1k
FAIL
PASS/
FAIL
1/6
LDAC
LDAC
IN
LDAC
LDAC
input is
REV. A
1k
PASS