AD7568 Analog Devices, AD7568 Datasheet - Page 4

• Manufacturer Part Number: AD7568
• Description: Octal 12-Bit CMOS DAC
• Manufacturer: Analog Devices

Specifications of AD7568

• Resolution (bits): 12bit
• Dac Update Rate: 2MSPS
• Dac Settling Time: 500ns
• Max Pos Supply (v): +5.25V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser

AD7568
ABSOLUTE MAXIMUM RATINGS
T
Parameter
V
I
I
Digital Input Voltage to DGND
V
Input Current to Any Pin Except Supplies
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Power Dissipation (Any Package) to 75°C
Derates above 75°C by
1
Mnemonic
V
DGND
AGND
V
R
I
AGND
CLKIN
FSIN
SDIN
SDOUT
A0
LDAC
CLR
OUT1
OUT2
OUTA
Transient currents of up to 100 mA will not cause SCR latch-up.
DD
RFB
DD
REFA
FBA
A
Commercial Plastic (B Versions)
= 25°C, unless otherwise noted
, V
to DGND
to R
to DGND
to DGND
to V
to I
REF
OUTH
REFH
FBH
to DGND
Description
Positive Power Supply. This is 5 V ± 5%.
Digital Ground.
Analog Ground
DAC Reference Inputs.
DAC Feedback Resistor Pins.
DAC Current Output Terminals.
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it
enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low.
Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally
comes the three DAC select bits. These determine which DAC in the device is selected for loading.
This shift register output allows multiple devices to be connected in a daisy-chain configuration.
Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the
data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the
input latches.
Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.
1
Rating
−0.3 V to +6 V
−0.3 V to V
−0.3 V to V
−0.3 V to V
±15 V
±10 mA
−40°C to +85°C
−65°C to +150°C
300°C
10 mW/°C
250 mW
DD
DD
DD
+0.3 V
+0.3 V
+0.3 V
PIN DESCRIPTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
– 4 –
REV. C