AD667 Analog Devices, AD667 Datasheet - Page 8

no-image

AD667

Manufacturer Part Number
AD667
Description
Microprocessor-Compatible 12-Bit D/A Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD667

Resolution (bits)
12bit
Dac Update Rate
500kSPS
Dac Settling Time
2µs
Max Pos Supply (v)
+16.5V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Byte,Nibble,Par

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD6671ABBCZ-740
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD6672BCPZ-250
Manufacturer:
SMSC
Quantity:
869
Part Number:
AD6674BCPZ-750
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6674BCPZ-750
Quantity:
358
Part Number:
AD667AD
Manufacturer:
AD
Quantity:
1 520
Part Number:
AD667AD
Manufacturer:
ADI
Quantity:
75
Part Number:
AD667AE
Manufacturer:
a
Quantity:
1
Part Number:
AD667AE
Manufacturer:
ADI
Quantity:
147
Part Number:
AD667BD
Manufacturer:
AD
Quantity:
125
Part Number:
AD667BD
Manufacturer:
ADI
Quantity:
72
Part Number:
AD667BD
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD667BE
Manufacturer:
S
Quantity:
8
Part Number:
AD667JN
Manufacturer:
AD
Quantity:
5 510
Part Number:
AD667JN
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD667JNZ
Manufacturer:
PSPR
Quantity:
6 220
Part Number:
AD667JNZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD667
Right-justified data can be similarly accommodated. The over-
lapping of data lines is reversed, and the address connections
are slightly different. The AD667 still occupies two adjacent
locations in the processor’s memory map. In the circuit of Fig-
ure 9, location X01 loads the 8 LSBs and location X10 loads
the 4 MSBs and updates the output.
USING THE AD667 WITH 12- AND 16-BIT BUSES
The AD667 is easily interfaced to 12- and 16-bit data buses. In
this operation, all four address lines (A0 through A3) are tied
Figure 9. Right-Justified 8-Bit Bus Interface
28-Pin Plastic DIP (N)
28-Contact LCC (E)
Dimensions shown in inches and (mm).
OUTLINE DIMENSIONS
–8–
low, and the latch is enabled by CS going low. The AD667 thus
occupies a single memory location.
This configuration uses the first and second rank registers
simultaneously. The CS input can be driven from an active-low
decoded address. It should be noted that any data bus activity
during the period when CS is low will cause activity at the
AD667 output. If data is not guaranteed stable during this
period, the second rank register can be used to provide double
buffering.
Figure 10. Connections for 12- and 16-Bit Bus Interface
28-Pin Ceramic DIP (D)
28-Terminal Plastic Leaded
Chip Carrier (P)
REV. A

Related parts for AD667