STA32813TR STMicroelectronics, STA32813TR Datasheet - Page 33

• Manufacturer Part Number: STA32813TR
• Description: IC DAS 2.1CH HI EFF POWERSO36
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Ampr

Specifications of STA32813TR

• Mounting Type: Surface Mount
• Package / Case: 36-PowerSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 497-8876-2

STA328
6.7
6.7.1
Note:
6.7.2
6.7.3
Volume control
Master controls
Master mute register (addr 0x06)
Master volume register (addr 0x07)
Value of volume derived from MVOL is dependent on AMV AutoMode volume settings.
Channel controls
Channel 1 volume (addr 0x08)
Channel 2 volume (addr 0x09)
Channel 3 volume (addr 0x0A)
Volume description
The volume structure of the STA328 consists of individual volume registers for each of the
three channels and a master volume register, and individual channel volume trim registers.
The channel volume settings are normally used to set the maximum allowable digital gain
and to hard-set gain differences between certain channels. These values are normally set at
the initialization of the IC and not changed. The individual channel volumes are adjustable in
0.5-dB steps from +48 dB to -80 dB. The master volume control is normally mapped to the
master volume of the system. The values of these two settings are summed to find the
actual gain/volume value for any given channel.
When set to 1, the master mute will mute all channels, whereas the individual channel
mutes (CxM) will mute only that channel. Both the master mute and the channel mutes
provide a “soft mute” with the volume ramping down to mute in 4096 samples from the
maximum volume setting at the internal processing rate (approximately 96 kHz). A “hard
Reserved
C1V7
C2V7
C3V7
MV7
D7
D7
D7
D7
D7
1
0
0
0
0
Reserved
MV6
C1V6
C2V6
C3V6
D6
D6
D6
D6
D6
1
0
1
1
1
Reserved
MV5
C1V5
C2V5
C3V5
D5
D5
D5
D5
1
D5
0
1
1
1
Reserved
MV4
C1V4
C2V4
C3V4
D4
1
D4
D4
D4
D4
0
0
0
0
Reserved
MV3
D3
C1V3
C2V3
C3V3
1
D3
D3
D3
D3
0
0
0
0
Reserved
MV2
D2
C1V2
C2V2
C3V2
1
D2
D2
D2
D2
0
0
0
0
Register description
Reserved
MV1
C1V1
C2V1
C3V1
D1
D1
1
D1
D1
D1
0
0
0
0
MMUTE
C1V0
C2V0
C3V0
MV0
D0
D0
D0
D0
D0
1
0
0
0
0
33/57