ADUC814 Analog Devices, ADUC814 Datasheet - Page 42

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

ADuC814
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the supply (DV
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.63 V. For correct operation
of the power supply monitor function, DV
or greater than 2.7 V. Monitor function is controlled via the
PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
interrupts the core using the PSMI bit in the PSMCON SFR.
PSMCON
SFR Address
Power-On Default
Bit Addressable
Table 16. PSMCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
----
Name
PSMCON.7
CMPD
PSMI
TPD1
TPD0
PSMCON.2
PSMCON.1
PSMEN
CMPD
DD
Description
Reserved.
DV
This is a read-only bit and directly reflects the state of the DV
Read 1 indicates that the DV
Read 0 indicates that the DV
Power Supply Monitor Interrupt Bit.
This bit is set high by the MicroConverter if CMPD is low, indicating low digital supply. The PSMI bit can be used to
interrupt the processor. Once CMPD returns and remains high, a 250 ms counter is started. When this counter
times out, the PSMI interrupt is cleared. PSMI can also be written by the user; however, if the comparator output is
low, it is not possible for the user to clear PSMI.
DV
These bits select the DV
TPD1
0
0
1
1
Reserved.
Reserved.
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
) on the ADuC814. It indicates when
DD
DD
DEH
No
Power Supply Monitor Control Register
DFH
Comparator Bit.
Trip Point Selection Bits.
PSMI
DD
TPD0
0
1
0
1
must be equal to
DD
trip-point voltage as follows:
DD
DD
supply is above its selected trip point.
supply is below its selected trip point.
TPD1
Rev. A | Page 42 of 72
Selected DV
4.63
3.08
2.93
2.63
This bit is not cleared until the failing power supply has
returned above the trip point for at least 250 ms. This monitor
function allows the user to save working registers to avoid
possible data loss due to the low supply condition, and also
ensures that normal code execution does not resume until a safe
supply level is well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
TPD0
DD
Trip Point (V)
DD
comparator.
----
----
PSMEN