ADUC814 Analog Devices, ADUC814 Datasheet - Page 59

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

Interrupt Priority
The interrupt enable registers are written by the user to enable
individual interrupt sources, while the interrupt priority
registers allow the user to select one of two priority levels for
each interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed as shown in Table 32.
Table 32. Priority within an Interrupt Level
Source
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI
RI + TI
TF2 + EXF2
TII
Priority
1 (Highest)
2
3
4
5
6
7
8
9
10
11 (Lowest)
Power Supply Monitor Interrupt
Serial Interrupt
Timer/Counter 2 Interrupt
Description
Watchdog Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI Interrupt
Time Interval Counter Interrupt
Rev. A | Page 59 of 72
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 33.
Table 33. Interrupt Vector Addresses
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADC)
ISPI
PSMI
TII
WDS (WDIR = 1)
1
when it times out. This is used for logging errors or to examine the internal
status of the microcontroller core to understand, from a software debug point
of view, why a watchdog timeout occurred. The watchdog interrupt is slightly
different from normal interrupts in that its priority level is always set to 1, and
it is not possible to disable the interrupt via the global disable bit (EA) in the IE
SFR. This is done to ensure that the interrupt is always responded to if a
watchdog timeout occurs. The watchdog produces an interrupt only if the
watchdog timeout is greater than zero.
The watchdog can be configured to generate an interrupt instead of a reset
1
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
ADuC814