ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 32

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
When the ADC starts a conversion (see Figure 19), SW3 opens,
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected as soon as
the conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to return the comparator to
a balanced condition. When the comparator is rebalanced, the
conversion is complete.
The control logic generates the ADC output code. The output
impedances of the sources driving the V
input must be matched; otherwise, the two inputs have different
settling times, resulting in errors.
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the V
input of the ADuC7121, and SW2 switches between A
(Channel−) and B (V
ground or a low voltage. The input signal on V
from V
V
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The V
range on V
AIN11
AIN11
AIN11
AIN0
AIN0
AIN0
V
REF
IN–
+ V
MUX
MUX
MUX
IN−
IN−
to V
IN+
does not exceed AV
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
Figure 20. ADC in Pseudo Differential Mode
is 0 V to V
REF
IN−
+ V
input pin can be floating. The input signal
Figure 18. ADC Acquisition Phase
Figure 19. ADC Conversion Phase
B
A
A
B
REF
B
A
A
B
B
A
A
B
IN−
V
V
V
REF
REF
REF
SW1
SW2
SW1
SW2
SW1
SW2
). The V
. Note that V
REF
.
C
C
C
C
C
C
S
S
S
S
S
S
DD
IN−
.
input must be connected to
SW3
IN−
SW3
SW3
COMPARATOR
IN+
COMPARATOR
COMPARATOR
must be chosen so that
input and the V
IN+
can then vary
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
CONTROL
DAC
LOGIC
DAC
DAC
LOGIC
DAC
DAC
LOGIC
DAC
IN−
IN−
Rev. 0 | Page 32 of 96
AIN11
Analog Input Structure
Figure 22 shows the equivalent circuit of the analog input structure
of the ADC. The four diodes provide ESD protection for the analog
inputs. Take care to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. Voltage in excess
of 300 mV causes these diodes to become forward biased and to
start conducting into the substrate. These diodes can conduct
up to 10 mA without causing irreversible damage to the part.
The C1 capacitors in Figure 22 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of
16 pF typical.
For ac applications, removing high frequency components from
the analog input signal is recommended with an RC low-pass
filter on the relevant analog input pins. In applications where
harmonic distortion and signal-to-noise ratio are critical, drive
the analog input from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and can necessitate the use of an input buffer amplifier. The choice
of the op amp is a function of the particular application. Figure 23
and Figure 24 give an example of an ADC front end.
Figure 22. Equivalent Analog Input Circuit Conversion Phase: Switches Open,
AIN0
MUX
Figure 23. Buffering Single-Ended/Pseudo Differential Input
CHANNEL+
C1
C1
Figure 21. ADC in Single-Ended Mode
CHANNEL–
Track Phase: Switches Closed
B
A
SW1
AV
AV
DD
DD
10Ω
D
D
D
D
0.01µF
C
C
S
S
SW3
R1 C2
R1 C2
ADuC7121
ADC0
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC