ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 73

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

SERIAL PERIPHERAL INTERFACE
The ADuC7121 integrates a complete hardware serial peri-
pheral interface (SPI) on-chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to
be synchronously transmitted and simultaneously received,
that is, full duplex up to a maximum bit rate of 20 Mbps.
The SPI port can be configured for master or slave operation
and typically consists of four pins: P0.3/MISO/PLAO[12]/SYNC,
P0.4/MOSI/PLAI[11]/TRIP, P0.2/SPICLK/ADC
and P0.5/ CS /PLAI[10]/ ADC
SPI MISO (MASTER IN, SLAVE OUT) PIN
MISO on the P0.3/MISO/PLAO[12]/SYNC pin is configured as
an input line in master mode and an output line in slave mode.
Connect the MISO line on the master (data in) to the MISO line
in the slave device (data out). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SPI MOSI (MASTER OUT, SLAVE IN) PIN
MOSI on the P0.4/MOSI/PLAI[11]/TRIP pin is configured as
an output line in master mode and an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is transferred
as byte wide (8-bit) serial data, MSB first.
SPICLK (SERIAL CLOCK I/O) PIN
The master serial clock (SPICLK) synchronizes the data being
transmitted and received through the MOSI SPICLK period.
Therefore, a byte is transmitted/received after eight SPICLK
periods. The P0.2/SPICLK/ADC
as an output in master mode and as an input in slave mode.
In master mode, the polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the SPIDIV
register as follows:
The maximum speed of the SPI clock is independent on the
clock divider bits.
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10 Mbps.
In both master and slave modes, data is transmitted on one edge
of the SPICLK signal and sampled on the other. Therefore, it is
f
SERIAL
CLOCK
=
2
×
1 (
+
f
UCLK
SPIDIV
CONVST
BUSY
.
/PLAO[13] pin is configured
)
BUSY
/PLAO[13],
Rev. 0 | Page 73 of 96
important that the polarity and phase are configured the same
for the master and slave devices.
SPI CHIP SELECT INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of CS
on the P0.5/ CS /PLAI[10]/ADC
input signal. The SPI port then transmits and receives 8-bit data
until the transfer is concluded by deassertion of CS . In slave
mode, CS is always an input.
In SPI master mode, CS is an active low output signal. It asserts
itself automatically at the beginning of a transfer and deasserts
itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC7121 device are P0.2 to P0.5.
•
•
•
•
To configure P0.2 to P0.5 for SPI mode, see the
General-Purpose Input/Output section.
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA,
SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
This 32-bit MMR contains the status of the SPI interface in both
master and slave modes.
Name:
Address:
Default value:
Access:
P0.5/ CS /PLAI[10]/ADC
slave mode, this pin is an input and must be driven low by
the master. In master mode, this pin is an output and goes
low at the beginning of a transfer and high at the end of a
transfer.
P0.2/SPICLK/ADC
P0.3/MISO/PLAO[12]/SYNC is the master in, slave out pin.
P0.4/MOSI/PLAI[11]/TRIP is the master out, slave in pin.
SPISTA
0xFFFF0A00
0x0000
Read only
BUSY
/PLAO[13] is the SPICLK pin.
CONVST
CONVST
is the slave chip select pin. In
pin. CS is an active low
ADuC7121