ADP120 Analog Devices, ADP120 Datasheet - Page 4

• Manufacturer Part Number: ADP120
• Description: 100 mA, Low Quiescent Current, CMOS Linear Regulator
• Manufacturer: Analog Devices

ADP120
Parameter
POWER SUPPLY REJECTION RATIO
1
2
3
4
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE
CAPACITOR ESR
1
Based on an endpoint calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
Start-up time is defined as the time between the rising edge of EN to V
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
Symbol
PSRR
1
Conditions
10 kHz, V
10 kHz, V
10 kHz, V
OUT
IN
IN
IN
Symbol
C
R
Rev. B | Page 4 of 20
= 5 V, V
= 5 V, V
= 5 V, V
ESR
being at 90% of its nominal value.
MIN
OUT
OUT
OUT
= 3.3 V
= 2.5 V
= 1.2 V
Conditions
T
T
A
A
= −40°C to +125°C
= −40°C to +125°C
Min
Min
0.70
0.001
Typ
60
66
70
Typ
Max
Max
1
Unit
dB
dB
dB
Unit
μF
Ω