STA308A STMicroelectronics, STA308A Datasheet
STA308A
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STA308A Summary of contents
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... Max power correction for lower full-power THD ! Variable per channel DDX ! 192 kHz internal processing sample rate, 24-bit to 36-bit precision Description The STA308A is a single chip solution for digital audio processing and control in multi-channel applications. It provides output capabilities for ® DDX (direct digital amplification). In conjunction ® ...
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... Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Configuration register A (0x00 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 23 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 25 Configuration register D (0x03 Configuration register E (0x04 Configuration register F (0x05 STA308A ...
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... STA308A 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 7.2.43 Configuration register G (0x06 Configuration register H (0x07) ...
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... Coefficient a2 data register, bits 23:16 (0x46 Coefficient a2 data register, bits 15:8 (0x47 Coefficient a2 data register, bits 7:0 (0x48 Coefficient b0 data register, bits 23:16 (0x49 Coefficient b0 data register, bits 15:8 (0x4A Coefficient b0 data register, bits 7:0 (0x4B Coefficient write control register (0x4C STA308A ...
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... STA308A 7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2.1 8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.1 8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.4.1 8.4.2 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 61 11 Revision history ...
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... Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Thermal data Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. Register summary Table 9. RAM block for biquads, mixing, and bass management Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6/63 STA308A ...
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... Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Pin connection (Top view Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Reference schematic for STA308A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 9. TQFP64 ( 1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 58 List of figures ...
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... SAMPLING SDO78 Volume 2x Mix #2 Limiter Interp DDX Output PWM Biquad Biquad Biquad Bass # User Programmable Hard Set Hard Set Coeffecients when Coeffecients when Biquads #9 and #10 When Tone Bypassed AutoMode DeEmphasis (CxTCB) Bass Management Enabled Crossover (DEMP) (AMBMXE) STA308A To Mix#2 Engine Treble ...
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... NC 36 GND 35 VDD 34 OUT6_A 33 OUT6_B STA308APINCON Description Master volume override/ DSD input clock Input serial data channels 7 & 8/ DSD input channel 6 Input serial data channels 5 & 6/ DSD input channel 5 Input serial data channels 3 & 4/ DSD input channel 4 Input serial data channels 1 & 2/ ...
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... FILTER_PLL GNDA CKOUT OUT8B OUT8A OUT7B OUT7A OUT6B OUT6A OUT5B OUT5A OUT4B OUT4A OUT3B OUT3A OUT2B STA308A Description 2 Select address ( Serial data ( Serial clock (I C) Crystal oscillator input (clock input) PLL filter PLL ground PLL supply Clock output PWM channel 8 output B ...
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... STA308A Table 2. Pin description (continued) Pin 3.3-V capable TTL 2mA 48 output buffer 3.3-V capable TTL 2mA 49 output buffer 3.3-V capable TTL 2mA 50 output buffer 3.3-V capable TTL 4mA 51 output buffer 3.3-V capable TTL 2mA 55 output buffer 3.3-V capable TTL 2mA 56 output buffer 3 ...
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... Recommended operating condition Table 5. Recommended operating condition Symbol V I/O power supply DD V Logic power supply DDA T Operating junction temperature j 12/63 Parameter -0.5 -40 -40 Parameter Parameter 3.0 -40 STA308A Min Typ Max Unit VDD + -0.5 V 0.5 VDD + -0.5 V 0.3 150 °C 90 °C ...
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... STA308A 3.4 Electrical specifications The following specifications are valid for VDD = 3.3V ± 0.3V, VDDA = 3.3V ± 0.3V and Tamb = °C, unless otherwise stated Table 6. General interface electrical specifications Symbol I Low-level input no pull-up il High-level input pull-down Tristate output leakage I OZ without pull-up/down ...
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... These are the outputs for audio information. Six different formats are available including I left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. Device power-down (PWDN) Pulling PWDN low begins the power-down sequence which puts the STA308A into a low-power state. EAPD (pin 51) goes low approximately 30 ms later. 14/63 ...
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... Data input During the data input the STA308A samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...
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... Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA308A acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA308A again responds with an acknowledgement. ...
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... STA308A 6 Application reference schematic Figure 6. Reference schematic for STA308A-based application OUT1_B OUT7_A 49 32 OUT1_A OUT7_B 50 31 EAPD OUT8_A 51 30 VDD3.3_6 OUT8_B 52 29 GND_6 VDD3.3_3 GND_3 54 27 BICKO LRCKO CKOUT 56 25 SDO_12 VDD3.3_PLL 57 24 SDO_34 GNDA_PLL 58 23 VDD3.3_7 VDDA_PLL 59 22 GND_7 PLL_FILTER ...
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... C2VT1 C3VT3 C3VT2 C3VT1 C4VT3 C4VT2 C4VT1 C5VT3 C5VT2 C5VT1 C6VT3 C6VT2 C6VT1 C7VT3 C7VT2 C7VT1 C8VT3 C8VT2 C8VT1 C1IM2 C1IM1 STA308A D0 MCS0 SAI0 SAO0 OM0 C1BO HPB PWMD NSBW PSCE MMUTE MV0 C1V0 C2V0 C3V0 C4V0 C5V0 C6V0 C7V0 C8V0 ...
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... STA308A Table 8. Register summary (continued) Addr Name 0x1C C34im 0x1D C56im 0x1E C78im AutoMode 0x1F Auto1 0x20 Auto2 0x21 Auto3 0x22 PreEQ 0x23 Ageq 0x24 Bgeq 0x25 Cgeq 0x26 Dgeq 0x27 Egeq Processing loop 0x28 BQlp 0x29 MXlp Processing pypass 0x2A ...
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... C5B10 C5B9 C5B3 C5B2 C5B1 WA DCC11 DCC10 DCC9 DCC3 DCC2 DCC1 RCV7 RCV6 RCV5 CNV11 CNV10 CNV9 CNV3 CNV2 CNV1 STA308A D0 C3OM0 C5OM0 C7OM0 CFA8 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 ...
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... Interpolation ratio select Bit The STA308A has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times time (pass-through). The oversampling ratio of this interpolation is determined by the IR bits DSPB IR1 IR0 ...
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... Pass-through Pass-through DSD to 176.4 kHz conversion RST Name DSP bypass bit: DSPB 0: normal operation 1: bypass of biquad and bass/treble functions COS[1,0] PLL output PLL output / 4 PLL output / 8 PLL output / 16 STA308A st 1 stage interpolation ratio Description CKOUT frequency ...
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... Serial data interface The STA308A audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA308A always acts a slave when receiving audio input from standard digital audio components. Serial data for eight channels is provided using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1 and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin 7), and serial data 7 and 8 SDI78 (pin 6) ...
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... Registers The table below lists the serial audio input formats supported by STA308A as related to BICKI = fs, 192 kHz. BICKI 24/ where sampling rate 32, 44.1, 48, 88.2, 96, 176. SAI [3:0] SAIFB 1100 X I 1110 X Left/right-justified 16-bit data 0100 X I 0100 X I 1000 X I 0100 0 MSB-first I 1100 ...
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... RW 0 The STA308A features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sample frequency (fs) is also equivalent to the input sample frequency ...
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... RST Name Max power correction: setting of 1 enables STA50x MPC correction for THD reduction near maximum power output CSZ0 OM1 0 1 Description Description Description STA308A D0 OM0 0 ...
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... RW 0 The STA308A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. If HPB = 1, then the filter that the high-pass filter utilizes is made available as user- programmable biquad#1 ...
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... PWMS[2:0] PWM speed selection: PWM output speed Normal speed (384 kHz) (all channels Half-speed (192 kHz) (all channels Double-speed (768 kHz) (all channels Normal speed (channels 1-6), double-speed (channels 7-8) Odd speed (341.3 kHz) (all channels) STA308A Description Description Description Description ...
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... SNR of AM radio. Bit The STA308A features a 2 DDX processing modes that minimize the amount of noise generated in frequency range of AM radio. This second mode is intended for use when DDX is operating in a device with an AM tuner active. This mode eliminates the noise-shaper. Bit RW 5 ...
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... Name Soft volume enable: SVE 1: volume adjustments use soft volume 0: volume adjustments occur immediately Name Zero-detect mute enable: setting of 1 enables the ZDE automatic zero-detect mute Description Description SVE ZCE 1 1 Description Description Description Description STA308A D0 NSBW 0 ...
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... STA308A Bit Setting the IDE bit enables this function, which looks at the input I automatically mute if the signals are perceived as invalid. Bit Detects loss of input MCLK in binary mode and will output 50% duty cycle. Bit Actively prevents double trigger of LRCLK. Bit When active will issue a device power down signal (EAPD) on clock loss detection 7 ...
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... C3V6 0 1 7.2.15 Channel 4 volume (0x0E C4V7 C4V6 0 1 32/ MV5 MV4 MV3 C1V5 C1V4 C1V3 C2V5 C2V4 C2V3 C3V5 C3V4 C3V3 C4V5 C4V4 C4V3 STA308A MMUTE MV2 MV1 MV0 C1V2 C1V1 C1V0 C2V2 C2V1 C2V0 C3V2 C3V1 C3V0 C4V2 C4V1 C4V0 ...
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... STA308A 7.2.16 Channel 5 volume (0x0F C5V7 C5V6 0 1 7.2.17 Channel 6 volume (0x10 C6V7 C6V6 0 1 7.2.18 Channel 7 volume (0x11 C7V7 C7V6 0 1 7.2.19 Channel 8 volume (0x12 C8V7 C8V6 0 1 7.2.20 Channel 1 volume trim, mute, bypass (0x13 C1M C1VBP 0 0 7.2.21 Channel 2 volume trim, mute, bypass (0x14) ...
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... C8VBP 0 0 The volume structure of the STA308A consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. There is also an additional offset for each channel called the channel volume trim. The individual channel volumes are adjustable in 0.5 dB steps from + -78 dB example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for channel ...
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... STA308A When ZCE = 0, volume updates occur immediately. Each channel also contains an individual channel volume bypass particular channel has volume bypassed via the CnVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute ...
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... S can be mapped to any internal processing channel via the 2 S input channel to its corresponding processing channel. CnIM[2:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel C1IM2 C1IM1 C3IM2 C3IM1 C5IM2 C5IM1 C7IM2 C7IM1 1 1 Serial input from STA308A D0 C1IM0 0 D0 C3IM0 0 D0 C5IM0 0 D0 C7IM0 0 ...
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... STA308A 7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F AMDM AMGC2 0 0 Bit RW 1 setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-6 becomes hard-set to -18 dB. ...
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... AutoMode bass management mix disabled AMBMME 1: AutoMode bass management mix enabled RST Name 0: AutoMode bass management crossover disabled AMBMXE 1: AutoMode bass management crossover enabled Bitfield Off Off FSS AMBMXE 0 0 Description Description nd order 10 01 Large Small Large Small STA308A D0 AMBMME 0 00 ...
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... STA308A FSS - front speaker size SUB - subwoofer When AMBMXE = 1, biquad #7 on channels 1-6 are utilized for bass-management crossover filter, this biquad is not user programmable in this mode. The XO settings determine the crossover frequency used, the crossover is 2 low-pass with cross point. Higher order filters can be obtained be programming coefficients in other biquads if desired ...
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... PEQ4 PEQ3 XO[2: 100 Hz 110 Hz 120 Hz 140 Hz 160 Hz PEQ[4:0] Flat Rock Soft Rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-Hop Dialog Bass-boost #1 Bass-boost #2 Bass-boost #3 Loudness 1 Loudness 2 Loudness 3 Loudness PEQ2 PEQ1 0 0 Bass management crossover frequency Mode / setting STA308A D0 PEQ0 0 ...
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... STA308A 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 7.2.36 AGEQ - graphic EQ 80-Hz band (0x23 7.2.37 BGEQ - graphic EQ 300-Hz band (0x24 7.2.38 CGEQ - graphic EQ 1-kHz band (0x25 7.2.39 DGEQ - graphic EQ 3-kHz band (0x26 Loudness 5 Loudness 6 Loudness 7 Loudness 8 ...
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... EGEQ3 0 1 xGEQ[4:0] +16 +15 +14 … … -14 - C6BLP C5BLP C4BLP Name For input from channel n MIX#1 engine output - normal CnBLP operation 1: input from channel ( biquad #10 output - loop operation EGEQ2 EGEQ1 1 1 Boost / cut D2 D1 C3BLP C2BLP 0 0 Description STA308A D0 EGEQ0 1 D0 C1BLP 0 ...
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... STA308A 7.2.42 Mix internal channel loop-through (0x29 C8MXLP C7MXLP 0 0 Each internal processing channel can receive two possible sets of inputs at the inputs to the Mix#1 block. The inputs can come from the outputs of the interpolation block as normally occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel ...
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... Limiter 1 attack/release rate (0x2F L1A3 L1A2 0 1 44/ TTC1 TTC0 BTC3 -12 dB -12 dB … … +12 dB +12 dB +12dB C3LS1 C3LS0 C2LS1 C7LS1 C7LS0 C6LS1 L1A1 L1A0 L1R3 STA308A BTC2 BTC1 BTC0 Boost / cut C2LS0 C1LS1 C1LS0 C6LS0 C5LS1 C5LS0 L1R2 L1R1 L1R0 ...
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... The limiter attack thresholds are determined by the LnAT registers recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within the STA308A it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain ...
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... Attenuation CnLS[1,0] Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 LnA[3:0] 3.1584 (fast) 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 (slow) STA308A RMS Output Saturation Channel limiter mapping Attack rate (dB/ms) ...
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... STA308A 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LnR[3:0] 0.5116 (fast) 0.1370 0.0744 0.0499 0.0360 0.0299 ...
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... LnRT[3:0] -∞ -29 dB -20 dB -16 dB -14 dB - LnAT[3:0] -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 - Anti-clipping (AC) (dB relative to FS) Dynamic range compression (DRC) (dB relative to volume) STA308A ...
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... STA308A 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.2.53 Channel 1 and 2 output timing (0x33 C2OT2 1 7.2.54 Channel 3 and 4 output timing (0x34 C4OT2 1 7.2.55 Channel 5 and 6 output timing (0x35 C6OT2 1 LnRT[3:0] -∞ -38 dB ...
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... Channel I S output mapping channels 5 and 6 (0x39 C6OM2 1 50/ C8OT1 C8OT0 1 1 CnOT[2: C2OM1 C2OM0 C4OM1 C4OM0 C6OM1 C6OM0 C7OT2 C7OT1 0 1 PWM slot C1OM2 C1OM1 C3OM2 C3OM1 C5OM2 C5OM1 1 0 STA308A D0 C7OT0 1 D0 C1OM0 0 D0 C3OM0 0 D0 C5OM0 0 ...
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... STA308A 2 7.2.60 Channel I S output mapping channels 7 and 8 (0x3A C8OM2 1 2 Each I S output channel can receive data from any channel output of the volume block. Which channel a particular I register bits. 000 001 010 011 100 101 110 111 7.2.61 Coefficient address register 1 (0x3B) ...
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... C1B12 C1B11 C1B5 C1B4 C1B3 C2B21 C2B20 C2B19 C2B13 C2B12 C2B11 C2B5 C2B4 C2B3 C1B21 C1B20 C1B19 C3B13 C3B12 C3B11 STA308A C1B10 C1B9 C1B8 C1B2 C1B1 C1B0 C2B18 C2B17 C2B16 C2B10 C2B9 C2B8 C2B2 C2B1 C2B0 C1B18 C1B17 C1B16 C3B10 C3B9 ...
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... STA308A 7.2.71 Coefficient a1 data register, bits 7:0 (0x45 C3B7 C3B6 0 0 7.2.72 Coefficient a2 data register, bits 23:16 (0x46 C4B23 C4B22 0 0 7.2.73 Coefficient a2 data register, bits 15:8 (0x47 C4B15 C4B14 0 0 7.2.74 Coefficient a2 data register, bits 7:0 (0x48 C4B7 C4B6 0 0 7.2.75 ...
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... Registers 7.2.78 Coefficient write control register (0x4C Coefficients for EQ and Bass Management are handled internally in the STA308A via RAM. Access to this RAM is available to the user via collection registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to RAM ...
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... When using this technique, the 10-bit address would specify the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA308A will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data ...
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... Figure 8. Channel mixer 8.1 Post-scale The STA308A provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is loaded into RAM using the same I biquad coefficients and the bass-management ...
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... STA308A Table 9. RAM block for biquads, mixing, and bass management (continued) Index (decimal … … 99 100 … 399 400 401 402 … 407 408 409 … 415 416 417 … 423 424 425 … 463 464 465 … 471 472 473 ...
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... Channel 8 - Mix MPCC13 MPCC12 MPCC11 MPCC5 MPCC4 MPCC3 DCC13 DCC12 DCC11 DCC5 DCC4 DCC3 Coefficient … … C8MX28 0x7FFFFF MPCC10 MPCC9 MPCC2 MPCC1 DCC10 DCC9 DCC2 DCC1 0 1 STA308A Default D0 MPCC8 1 D0 MPCC0 0 D0 DCC8 1 D0 DCC0 1 ...
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... STA308A 8.4 PSCorrect registers ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels. Though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. 8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) Equivalent to negative maximum ripple peak as a percentage of Vcc (MPR), scaled by the inverse of maximum ripple p-p as percentage of full-scale analog input to ADC ...
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... TQFP64 STA308A OUTLINE AND MECHANICAL DATA TQFP64 ( 1.4mm 0.08mm ccc Seating Plane C K 0051434 E ® ...
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... STA308A 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Trademarks and other acknowledgements 61/63 ...
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... Revision 1 Initial release. 2 Changed in page 4 value T 3 Changed in Figure 4 and Table 2 the name of the pins 22 and 24. Updated cover page Added chapter 6, Application reference schematic 4 Removed reserved registers from chapter 7 Updated register descriptions in chapter 7 Various minor changes. STA308A Changes and T . amb j ...
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... STA308A Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...