STA308A STMicroelectronics, STA308A Datasheet - Page 14

IC AUDIO PROCESSOR DGTL 64-TQFP

STA308A

Manufacturer Part Number
STA308A
Description
IC AUDIO PROCESSOR DGTL 64-TQFP
Manufacturer
STMicroelectronics
Series
DDX™r
Type
Audio Processorr
Datasheet

Specifications of STA308A

Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Lead Free Status / Rohs Status
Compliant

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Pin description
4
14/63
Pin description
Master volume override (MVO)
This pin enables the user to bypass the volume control on all channels. When MVO is pulled
high, the master volume register is set to 0x00, which corresponds to its full scale setting.
The master volume register setting offsets the individual channel volume settings, which
default to 0 dB.
Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)
Audio information enters the device here. Six format choices are available including I
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.
I
The SA, SDA and SCL pins operate per the Phillips I
Phase locked loop (PLL)
The phase locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by the CKOUT.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
External amplifier power-down (EAPD)
This signal can be used to control the power-down of DDX power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA308A into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.
2
C bus
2
C specification. See Section 5.
STA308A
2
S,
2
S,

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