E-TDA7590 STMicroelectronics, E-TDA7590 Datasheet - Page 25

• Manufacturer Part Number: E-TDA7590
• Description: IC DSP SPEECH/AUDIO 144-TQFP
• Manufacturer: STMicroelectronics
• Type: Signalr

Specifications of E-TDA7590

• Applications: Speech Recognition
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP Exposed Pad, 144-eTQFP, 144-HTQFP, 144-VQFP
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 384KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.62/3V
• Operating Supply Voltage (max): 1.98/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA7590
LOCK
OUTLOCK
MF0
MF1
MF2
MF3
MF4
MF5
MF6
PLLIE
PWRDN
DITEN
FRACEN
PEN
;;; Bit Definitions for PLL_CLKCNTL
DSPDF0
DSPDF1
DSPDF2
DSPDF3
; Reserved
DCKSRC
DACLKEN
MFSDF0
MFSDF1
MFSDF2
MFSDF3
MFSDF4
MFSDF5
MFSDF6
SEL0
SEL1
SEL2
DSP_XTI
DAC_SEL
XTLD
;------------------------------------------------------------------------
;
;------------------------------------------------------------------------
;
HDR
HDDR
PCRC
PRRC
PDRC
PCRD
PRRD
PDRD
PCRE
PRRE
PDRE
OGDB
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQUATES for I/O Port Programming
Register Addresses
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
1
2
3
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
$FFFFC9
$FFFFC8
$FFFFBF
$FFFFBE
$FFFFBD
$FFFFAF
$FFFFAE
$FFFFAD
$FFFF9F
$FFFF9E
$FFFF9D
$FFFFFC
; PLL Lock Indication bit
; PLL Lost Lock bit
; Multiplication bit 0
; Multiplication bit 1
; Multiplication bit 2
; Multiplication bit 3
; Multiplication bit 4
; Multiplication bit 5
; Multiplication bit 6
; PLL interrupt enable
; PLL power down
; Dither Enable
; PLL Fractional-N function enable
; PLL Enable
; DSP clock divider factor 0
; DSP clock divider factor 1
; DSP clock divider factor 2
; DSP clock divider factor 3
; DSP clock source 0->XTI/(DSPDF3:0 + 1)
;
; Enable bit for oversampling clock
; Oversampling multiple bit 0
; Oversampling multiple bit 1
; Oversampling multiple bit 2
; Oversampling multiple bit 3
; Oversampling multiple bit 4
; Oversampling multiple bit 5
; Oversampling multiple bit 6
; Sampling multiple select bit 0
; Sampling multiple select bit 1
; Sampling multiple select bit 2
; DSP_XTI =0 -> Use VCO/DSPDF
; DSP_XTI =1 -> Use XTI
; Selects between VCO and ext_dac_clk
; Disables the external crystal when set
; PS- Host port GPIO data Register
; PS- Host port GPIO direction Register
; Port C Control Register
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Register
; Port E Data Register
; OnCE GDB Register
1->VCO/(DSPDF3:0 + 1)
for DCLK
for DCLK
Appendix 1
25/42