STA304A STMicroelectronics, STA304A Datasheet - Page 28
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STA304A
Manufacturer Part Number
STA304A
Description
IC PROCESSOR AUD DGTL DDX 44TQFP
Manufacturer
STMicroelectronics
Series
DDX™r
Type
Audio Processorr
Datasheet
1.STA304A.pdf
(31 pages)
Specifications of STA304A
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Case
QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Applications
-
Other names
497-3944
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA304A
Manufacturer:
SANKEN
Quantity:
20 000
Company:
Part Number:
STA304A/STA304
Manufacturer:
pericom
Quantity:
11 120
STA304A
12.16BIST and Status Register (BASR) : add. 76h
12.17Coefficients Handling Registers (add. 78h – 7Ah)
See paragraph 10.
12.18Vendor ID Registers (add. 7Ch – 7Eh)
These registers are specific vendor identification for the STA304A. The Microsoft’s Plug and Play Vendor ID
code is "ALJ". The REV7.. 0 field is for the Vendor Revision number. These are read only registers, any write
request to one of these will be ignored.
28/31
DSP_BIS
T_Start
D15 D14 D13 D12 D11 D10
D15
BIT
10
11
12
13
14
15
AD7
D15
C15
0
1
2
3
4
5
6
7
8
9
0
0
DSP_BIS
T_Running
R/W
R/W
D14
I/F
W
W
R
R
R
R
R
R
R
R
R
R
R
R
AD6
D14
C14
1
1
DSP_BIS
T_Stop
DSP RST
D13
AD5
R
R
R
R
R
D13
C13
0
0
DSP_RA
D12
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AD4
D12
C12
0
0
M
DSP_BIST_Running
D11
AD3
D11
C11
DSP_BIST_Start
0
1
DSP_BIST_Stop
DDX_SPRAM_1
DDX_SPRAM_2
DDX_SPRAM_3
SRC_SPRAM_1
SRC_SPRAM_2
X
SPDIF_Status
DDX_DPRAM
SRC_Status
CH1_AMEN
AC3_AMEN
BIST_Start
BIST_Stop
DSP_RAM
NAME
D10
AD2
D10
C10
0
0
X
SRC_SP
RAM_2
D9
AD1
0
1
D9
D9
C9
SRC_SP
RAM_1
D8
AD0
When 0, the digital pll in the SRC is LOCKED. When 1 the digital
PLL is OUT of LOCK.
When 1, the SPDIF interface is out of lock. When 0 the interface
is locked to the SPDIF stream input.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enable automuting if AC3 frame header found
Enable automuting if no CH1_STATUS bit found
Reserved
Reserved
Reserved
Reserved
1
0
D8
D8
C8
REV7 REV6 REV5 REV4 REV3 REV2
DDX_DP
D7
R/W
0
RAM
D7
C7
D7
DDX_SP
D6
RAM_3
1
D6
C6
D6
DDX_SP
D5
RAM_2
0
D5
C5
D5
DESCRIPTION
DDX_SP
D4
RAM_1
0
D4
C4
D4
D3
BIST_St
C19
1
D3
C3
D3
op
C18
D2
BIST_St
D2
C2
1
D2
art
C17
D1
C1
REV1
SPDIF_
D1
Status
0
D1
C16
SRC_St
REV0
D0
C0
D0
atus
D0
0