TDF8555J NXP Semiconductors, TDF8555J Datasheet - Page 36

• Manufacturer Part Number: TDF8555J
• Description: The TDF8555J is one of a new generation of complementary quad Bridge-Tied Load(BTL) audio power amplifiers with full I²C-bus controlled diagnostics, multiple voltageregulator and two power switches intended for automotive applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 25.
Refer to test circuit (see
guaranteed for T
TDF8555J
Product data sheet
Symbol
t
t
t
t
t
t
t
t
I
V
V
V
f
Start-up diagnostics
t
t
V
R
d(mute_off)
amp_on
off
d(mute-on)
d(soft_mute)
d(fast_mute)
(start-Vo(off))
(start-SVRoff)
2
SCL
sudiag
d(sudiag-on)
C-bus interface
IL
IH
OL
offset
Ldet(sudiag)
Amplifier characteristics
Parameter
mute off delay time
amplifier on time
amplifier switch-off time
delay time from mute to on
soft mute delay time
fast mute delay time
engine start to output off
time
engine start to SVR off time
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
SCL clock frequency
start-up diagnostic time
start-up diagnostic to on
delay time
offset voltage
start-up diagnostic load
detection resistance
j
=
[3]

40

Figure
C to +150
29) at T

C; functionality guaranteed for V
…continued
amb
All information provided in this document is subject to legal disclaimers.
= 25
V
on pins SCL and SDA
on pins SCL and SDA
on pin SDA; I
from start-up diagnostic command via
Conditions
time from amplifier start until 10 % of
output signal; I
I
(IB1[D1] = 0); see
time from amplifier start until 90 % of
output signal; I
I
(IB1[D1] = 0); see
time to DC output voltage < 0.1 V;
I
see
from 10 % to 90 % of output signal;
V
from 90 % to 10 % of output signal;
V
from 90 % to 10 % of output signal;
V
in 1 s; IB2[D0] = 0 to 1
V
V
V
I
diagnostic; V
load) IB1[D1] = 1; see
at 90 % of output signal; IB1[D0:D1] = 11;
see
startup diagnostic offset voltage under no
load condition
shorted load
normal load
line driver load
open load
LO
LO
LO
2
i
i
i
P
o
P
SVR
C-bus until completion of start-up

Rev. 1 — 15 September 2011
high gain; IB3[D6:D5] = 00
low gain; IB3[D6:D5] = 11
high gain (IB3[D6:D5] = 00)
low gain (IB3[D6:D5] = 11)
= 50 mV; IB2[D1] = 1 to 0
= 50 mV; IB2[D1] = 0 to 1
= 50 mV; V
C; V
< 0.5 V; see
from 14.4 V to 5 V in 1.5 ms;
from 14.4 V to 5 V in 1.5 ms;
= 5 A  +15 ms; no DC-load
= 5 A  +30 ms; no DC-load
= 0 A; I
Figure 3
Figure 10
< 0.7 V; see
P
= 14.4 V; unless otherwise specified. Tested at T
4 45 W power amplifier with multiple voltage regulator
LO
O
L
STB
+ < 0.1 V; V
LO
LO
= 5 A  +0 ms;
= 5 mA
Figure 4
= 0 A;
= 0 A;
from > 2.5 V to < 0.8 V
Figure 3
Figure 3
Figure 4
P
Figure 10
< 10 V unless otherwise specified.
O
 < 0.1 V (no
[2]
[2]
[2]
Min
-
-
250
5
5
-
-
-
-
2.3
-
-
50
-
1.3
-
-
1.5
3.2
80
400
TDF8555J
Typ
430
550
500
15
15
0.4
0.1
40
-
-
-
400
130
680
2
-
-
-
-
-
-
amb
© NXP B.V. 2011. All rights reserved.
= 25
Max
650
800
750
40
40
1
1
75
1.5
5.5
0.4
-
250
-
2.5
0.5
1.5
20
20
200
-

C;
36 of 57
Unit
ms
ms
ms
ms
ms
ms
ms
ms
V
V
V
kHz
ms
ms
V





