LPC1112FHN33 NXP Semiconductors, LPC1112FHN33 Datasheet - Page 77

• Manufacturer Part Number: LPC1112FHN33
• Description: The LPC1112FHN33 is an ARM Cortex-M0 microcontroller and it can operate up to 50 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC111X
Product data sheet
10.6 I
Table 24.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] A Fast-mode I
Symbol
f
t
t
t
t
t
2
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
C-bus
See the I
Parameters are valid over operating temperature range unless otherwise specified.
t
and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
C
The maximum t
output stage t
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
The maximum t
the maximum of t
the device does not stretch the LOW period (t
data must be valid by the set-up time before it releases the clock.
t
transmission and the acknowledge.
t
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line t
Standard-mode I
meet this set-up time.
HD;DAT
SU;DAT
SU;DAT
= 40 C to +85 C.
IH
b
= total capacitance of one bus line in pF.
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
= 250 ns must then be met. This will automatically be the case if the device does not stretch the
Dynamic characteristic: I
2
C-bus specification UM10204 for details.
Parameter
SCL clock
frequency
fall time
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up
time
f
2
All information provided in this document is subject to legal disclaimers.
is specified at 250 ns. This allows series protection resistors to be connected in between the
C-bus device can be used in a Standard-mode I
HD;DAT
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
2
VD;DAT
C-bus specification) before the SCL line is released. Also the acknowledge timing must
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
[2]
or t
Rev. 7 — 1 March 2012
VD;ACK
[4][5][6][7]
[3][4][8]
[9][10]
by a transition time (see UM10204). This maximum must only be met if
2
C-bus pins
r(max)
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
of both SDA and
SCL signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
LPC1110/11/12/13/14/15
+ t
LOW
SU;DAT
) of the SCL signal. If the clock stretches the SCL, the
[1]
= 1000 + 250 = 1250 ns (according to the
32-bit ARM Cortex-M0 microcontroller
2
C-bus system but the requirement
Min
0
0
0
-
20 + 0.1  C
-
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
b
© NXP B.V. 2012. All rights reserved.
Max
100
400
1
300
300
120
-
-
-
-
-
-
-
-
-
-
-
-
f
.
77 of 103
Unit
kHz
kHz
MHz
ns
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns