LPC1114FN28 NXP Semiconductors, LPC1114FN28 Datasheet - Page 27
LPC1114FN28
Manufacturer Part Number
LPC1114FN28
Description
The LPC1114FN28 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/1
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1110FD20.pdf
(103 pages)
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NXP Semiconductors
[6]
Table 10.
LPC111X
Product data sheet
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package)
Pin
2
3
8
9
10
11
15
16
17
18
19
[2]
[3]
[3]
[3]
[4]
[4]
[3]
[3]
[3]
[3]
[3]
Start
logic
input
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Type Reset
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
O
I
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
state
[1]
I;PU
-
I;PU
-
-
I;PU
-
-
I;PU
I;PU
-
I;PU
-
I;PU
-
I;PU
-
I;PU
-
-
I;PU
-
-
I;PU
-
-
-
Rev. 7 — 1 March 2012
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends on
the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution
to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
CLKOUT — Clock out pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
if I
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I
I
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin (high-current
output driver).
CTS — Clear To Send input for UART.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SPI0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock.
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
2
C Fast-mode Plus is selected in the I/O configuration register.
2
C Fast-mode Plus is selected in the I/O configuration register.
2
2
C-bus, open-drain clock input/output. High-current sink only
C-bus, open-drain data input/output. High-current sink only if
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2012. All rights reserved.
27 of 103
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