LPC2210_2220 NXP Semiconductors, LPC2210_2220 Datasheet
LPC2210_2220
Related parts for LPC2210_2220
LPC2210_2220 Summary of contents
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LPC2210/2220 16/32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface Rev. 06 — 11 December 2008 1. General description The LPC2210/2220 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support. For critical ...
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... ARM7TDMI-S processor. 3. Ordering information Table 1. Type number LPC2210FBD144 LPC2210FBD144/01 LQFP144 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G LPC2210_2220_6 Product data sheet Ordering information Package Name Description LQFP144 plastic low profile quad flat package; 144 leads; body 20 plastic low profile quad flat package; 144 leads ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Type number LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G LPC2210_2220_6 Product data sheet Ordering options RAM Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers Fast GPIO/ Temperature range SSP/ Enhanced UART, ADC, Timer ...
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... A/D CONVERTER P0 P1 GENERAL P2 PURPOSE I/O P3 PWM[6:1] PWM0 (1) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (2) Shared with GPIO. (3) LPC2210/01 and LPC2220 only. Fig 1. Block diagram LPC2210_2220_6 Product data sheet (1) (1) TMS TDI (1) (1) (1) TRST TCK TDO TEST/DEBUG INTERFACE ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for LQFP144 Fig 3. Ball configuration diagram for TFBGA144 LPC2210_2220_6 Product data sheet 1 LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144 36 ball A1 LPC2220FET144 index area Transparent top view Rev. 06 — ...
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Table 3. Ball allocation Row Column P2.22/ V P1.28/ P2.21/ DDA(1V8) D22 TDI D21 B V P1.27/ XTAL2 V DD(3V3) SSA(PLL) TDO C P0.21/ V XTAL1 V SS SSA PWM5/ CAP1.3 D P0.24 P1.19/ P0.23 ...
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Table 3. Ball allocation …continued Row Column P0.29/ P0.30/ P1.16/ P0.0/ AIN2/ AIN3/ TRACEP TXD0/ CAP0.3/ EINT3/ KT0 PWM1 MAT0.3 CAP0.0 M P3.25/ P3.24/ V P1.31/ DD(3V3) CS2 CS3 TRST P3.23/ P3.21/ ...
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... CAP1.0 [1] P0.11/CTS1/ 83 CAP1.1 [1] P0.12/DSR1/ 84 MAT1.0 LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description I/O Port 0: Port 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. ...
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... MAT0.0 [1] P0.23 6 [1] P0.24 8 [1] P0.25 21 [4] P0.27/AIN0/ 23 CAP0.1/MAT0.1 LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description [1] H10 O DTR1 — Data Terminal Ready output for UART1. O MAT1.1 — Match output for Timer 1, channel 1. [2] G10 I DCD1 — Data Carrier Detect input for UART1. ...
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... PIPESTAT1 [5] P1.23/ 82 PIPESTAT2 [5] P1.24/ 70 TRACECLK [5] P1.25/EXTIN0 60 LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description [ AIN1 — ADC, input 1. This analog input is always connected to its pin. I CAP0.2 — Capture input for Timer 0, channel 2. O MAT0.2 — Match output for Timer 0, channel 2. ...
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... P2.22/D22 1 [5] P2.23/D23 10 [5] P2.24/D24 11 [5] P2.25/D25 12 LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description [5] N6 I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as Debug port after reset ...
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... P3.15/A15 55 [5] P3.16/A16 53 [5] P3.17/A17 48 [5] P3.18/A18 47 LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description [5] F4 I/O D26 — External memory data line 26. I BOOT0 — While RESET is LOW, together with BOOT1 controls booting and internal operation. Internal pull-up ensures HIGH state if pin is left unconnected. ...
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... 26, 38, SS 54, 67, 79, 93, 103, 107, 111, 128 V 139 SSA V 138 SSA(PLL) V 37, 110 DD(1V8) LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description [ A19 — External memory address line 19. [ A20 — External memory address line 20. [ A21 — External memory address line 21. ...
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... V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistor’s value ranges from 300 tolerant pad providing digital input (with TTL levels and hysteresis) function only. [7] Pad provides special analog functionality. LPC2210_2220_6 Product data sheet Pin (TFBGA) Type Description A2 I Analog 1 ...
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... The LPC2210/2220 memory maps incorporate several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either on-chip bootloader, external memory BANK0 or on-chip static RAM. This is described in Section 6.20 “System LPC2210_2220_6 Product data sheet control”. Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers © ...
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... Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. LPC2210_2220_6 Product data sheet 4.0 GB AHB PERIPHERALS 3 ...
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... I C SPI0 SPI1 and SSP PLL RTC System Control A/D LPC2210_2220_6 Product data sheet lists the interrupt sources for each peripheral function. Each peripheral device has Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only EmbeddedICE, DbgCommRX EmbeddedICE, DbgCommTX Match (MR0, MR1, MR2, MR3) ...
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... The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Settings other than those shown in Table 7. PINSEL0 1:0 3:2 5:4 7:6 9:8 LPC2210_2220_6 Product data sheet Pin control module registers Name Description PINSEL0 pin function select register 0 PINSEL1 pin function select register 1 PINSEL2 ...
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... NXP Semiconductors Table 7. PINSEL0 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 LPC2210_2220_6 Product data sheet Pin function select register 0 (PINSEL0 - 0xE002 C000) Pin name Value P0. ...
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... The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Settings other than those shown in the Table 8. PINSEL1 1:0 3:2 5:4 7:6 9:8 11:10 13:12 LPC2210_2220_6 Product data sheet Pin function select register 0 (PINSEL0 - 0xE002 C000) Pin name Value P0. ...
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... NXP Semiconductors Table 8. PINSEL1 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 LPC2210_2220_6 Product data sheet Pin function select register 1 (PINSEL1 - 0xE002 C004) Pin name Value P0. P0. P0. P0. P0. P0. ...
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... If bits 5:4 are not 10, controls the use of pin P2[29:28]: 0 enables P2[29:28 reserved 21 If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables AIN4 bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables AIN5. LPC2210_2220_6 Product data sheet Table 9 are reserved, and should not be used P2[ P3. P2[15: ...
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... Measurement range • Capable of performing more than 400000 10-bit samples per second. • Burst conversion mode for single or multiple inputs. LPC2210_2220_6 Product data sheet …continued 100 = A11 to A2 are address lines. 101 = A15 to A2 are address lines. 110 = A19 to A2 are address lines. ...
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... C-bus implemented in LPC2210/2220 supports a bit rate up to 400 kbit/s (fast 2 I C-bus). 6.13.1 Features • Compliant with standard I • Easy to configure as master, slave, or master/slave. LPC2210_2220_6 Product data sheet 2 C-bus interface. Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers 2 C-bus is a multi-master bus, and it © ...
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... Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. LPC2210_2220_6 Product data sheet 2 C-bus may be used for test and diagnostic purposes. ...
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... When counting cycles of an externally supplied clock, only one of the timer’s capture inputs can be selected as the timer’s clock. The rate of such a clock is limited to PCLK / 4. Duration of high/low levels on the selected capture input cannot be shorter than 1 / (2PCLK). LPC2210_2220_6 Product data sheet Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers © ...
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... Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge LPC2210_2220_6 Product data sheet 256 cy(PCLK) 4 ...
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... The oscillator output frequency is called f processor clock frequency is referred to as CCLK for purposes of rate equations, etc. f and CCLK are the same value unless the PLL is running and connected. Refer to 6.20.2 “PLL” LPC2210_2220_6 Product data sheet for additional information. Rev. 06 — 11 December 2008 ...
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... The LPC2210/2220 include up to nine edge or level sensitive external interrupt inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. LPC2210_2220_6 Product data sheet ramp (in the case of power on), the type of crystal DD Rev. 06 — ...
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... Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. LPC2210_2220_6 Product data sheet the processor clock rate ...
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... It communicates with the host using the debug communication channel, which is present in the EmbeddedICE logic. The LPC2210/2220 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2210_2220_6 Product data sheet 1 of the CPU clock (CCLK) for the JTAG 6 Rev. 06 — ...
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... Not to exceed 4.6 V. [7] Per supply pin. [8] The peak current is limited to 25 times the corresponding maximum current. [9] Per ground pin. [10] Dependent on package type. [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC2210_2220_6 Product data sheet [1] Conditions [2] [3] [4][ tolerant I/O pins [4][6] ...
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... OL I HIGH-level short circuit OHS output current I LOW-level short circuit OLS output current I pull-down current pd I pull-up current pu I active mode supply current DD(act) LPC2210_2220_6 Product data sheet Conditions pull- pull-down I DD(3V3 DD(3V3) no pull-up/down (0.5V ) < ...
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... Accounts for 100 mV voltage drop in all supply lines. [8] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [9] Minimum condition for V = 4.5 V, maximum condition for V I [10] Applies to P1[25:16]. [11 LPC2210_2220_6 Product data sheet …continued Conditions V = 1.8 V; DD(1V8 amb V = 1.8 V ...
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... See [7] The absolute voltage error ( the maximum difference between the center of the steps of the actual transfer curve of the T non-calibrated ADC and the ideal transfer curve. See LPC2210_2220_6 Product data sheet Conditions [1][2][3] [1][4] [1][5] ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC2210_2220_6 Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 ...
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... Parameters are valid over operating temperature range unless otherwise specified. [2] Bus capacitance C in pF, from 400 pF. b LPC2210_2220_6 Product data sheet Conditions supplied by an external oscillator (signal generator) external clock frequency supplied by an external crystal oscillator external clock frequency if ...
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... WE LOW to WE HIGH time WELWEH t BLS LOW to BLS HIGH time BLSLBLSH t WE HIGH to address invalid WEHANV time t WE HIGH to data invalid time WEHDNV t BLS HIGH to address invalid BLSHANV time LPC2210_2220_6 Product data sheet Conditions Min - - - - [ [2][ WST1)) + cy(CCLK) ...
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... Address valid to data valid. [6] Earliest of CS HIGH, OE HIGH, address change to data invalid. Table 15. Standard read access specifications Access cycle Max frequency standard read f standard write f burst read - initial f burst read - subsequent 3 f LPC2210_2220_6 Product data sheet Conditions Min [ earlier. cy(CCLK) WST setting WST 0 ...
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... NXP Semiconductors 9.1 Timing XCLK CS addr data t CSLOEL OE Fig 6. External memory read access XCLK CS BLS/WE addr data OE Fig 7. External memory write access LPC2210_2220_6 Product data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 06 — 11 December 2008 ...
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... Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) 1.8 V core (typical) (2) 1.65 V core (typical) Fig 9. LPC2210 I in Active mode measured at different frequencies (CCLK) and temperatures DD LPC2210_2220_6 Product data sheet t t CHCL CLCX 20 30 Rev. 06 — ...
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... Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register. (1) 1.95 V core (2) 1.8 V core (3) 1.65 V core Fig 11. LPC2210 I in Power-down mode measured at different temperatures DD LPC2210_2220_6 Product data sheet Rev. 06 — 11 December 2008 LPC2210/2220 ...
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... Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) 1.8 V core (typical) (2) 1.8 V core (typical) (3) 1.65 V core (typical) Fig 13. LPC2220 and LPC2210/01 I LPC2210_2220_6 Product data sheet Active mode measured at different frequencies (CCLK) and temperatures ...
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... A) 150 100 Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register. Fig 14. LPC2220 and LPC2210/01 I LPC2210_2220_6 Product data sheet Power-down mode measured at different temperatures DD Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers 002aad389 1 ...
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... max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT486-1 136E23 Fig 15. Package outline SOT486-1 (LQFP144) LPC2210_2220_6 Product data sheet ...
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... DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.05 0.35 0.70 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT569-2 Fig 16. Package outline SOT569-2 (TFBGA144) LPC2210_2220_6 Product data sheet scale ...
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... FIFO GPIO I/O JTAG PWM RISC SPI SSI SRAM TTL UART LPC2210_2220_6 Product data sheet Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Complex Instruction Set Computer First In, First Out General Purpose Input/Output Input/Output Joint Test Action Group ...
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... Product data sheet - Product data sheet - Product data sheet - Product data sheet - Preliminary data - Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers Supersedes LPC2210_2220_5 = 200 mV)”: removed i(RMS) 8. LPC2210_2220_4 LPC2210_2220_3 LPC2210_2220_2 LPC2210-01 - © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors product can reasonably be expected 14. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2210_2220_6 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC2210_2220_6 All rights reserved. Date of release: 11 December 2008 ...