LPC2212_2214 NXP Semiconductors, LPC2212_2214 Datasheet
LPC2212_2214
Related parts for LPC2212_2214
LPC2212_2214 Summary of contents
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LPC2212/2214 Single-chip 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC and external memory interface Rev. 5 — 14 June 2011 1. General description The LPC2212/2214 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace ...
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... CPU operating voltage range of 1. 1.95 V (1.8 V 0.15 V). I/O power supply range of 3 3.6 V (3.3 V with 5 V tolerant I/O pads. 3. Ordering information Table 1. Type number LPC2212FBD144/01 LPC2214FBD144/01 LPC2212_2214 Product data sheet Ordering information Package Name Description LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm LQFP144 plastic low profile quad flat package ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Type number LPC2212FBD144/01 LPC2214FBD144/01 LPC2212_2214 Product data sheet Ordering options Flash memory 128 kB 256 kB All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 LPC2212/2214 Single-chip 16/32-bit ARM microcontrollers RAM Fast GPIO/ Temperature range ...
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... SYSTEM CONTROL REAL-TIME CLOCK (1) Shared with GPIO. (2) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (3) SSP interface and high-speed GPIO are available on LPC2212/01 and LPC2214/01 only. Fig 1. Block diagram LPC2212_2214 Product data sheet (2) (2) TMS TDI RTCK ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning (1) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 2. Pin configuration (LQFP144) LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers 1 LPC2212 LPC2214 36 All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 ...
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... P0[11]/CTS1/CAP1[1] 83 P0[12]/DSR1/MAT1[0] 84 P0[13]/DTR1/MAT1[1] 85 LPC2212_2214 Product data sheet Type Description I/O Port 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not available. ...
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... MAT0[1] P0[28]/AIN1/CAP0[2]/ 25 MAT0[2] P0[29]/AIN2/CAP0[3]/ 32 MAT0[3] LPC2212_2214 Product data sheet Type Description I DCD1 — Data Carrier Detect input for UART1. I EINT1 — External interrupt 1 input. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after reset. ...
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... P2[2]/D2 106 P2[3]/D3 108 P2[4]/D4 109 P2[5]/D5 114 P2[6]/D6 115 LPC2212_2214 Product data sheet Type Description I AIN3 — ADC, input 3. This analog input is always connected to its pin. I EINT3 — External interrupt 3 input. I CAP0[0] — Capture input for Timer 0, channel 0. I/O Port 32-bit bidirectional I/O port with individual direction controls for each bit ...
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... P2[28]/D28 17 P2[29]/D29 18 P2[30]/D30/AIN4 19 P2[31]/D31/AIN5 20 P3[0] to P3[31] P3[0]/A0 89 P3[1]/A1 88 P3[2]/A2 87 LPC2212_2214 Product data sheet Type Description I/O External memory data line 7. I/O External memory data line 8. I/O External memory data line 9. I/O External memory data line 10. I/O External memory data line 11. I/O External memory data line 12. I/O External memory data line 13. ...
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... P3[29]/BLS2/AIN6 27 P3[30]/BLS1 97 P3[31]/BLS0 96 n.c. 22 RESET 135 XTAL1 142 XTAL2 141 LPC2212_2214 Product data sheet Type Description O External memory address line 3. O External memory address line 4. O External memory address line 5. O External memory address line 6. O External memory address line 7. O External memory address line 8. ...
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... V 14 DDA(3V3) [1] SSP interface is available on LPC2212/01 and LPC2214/01 only. LPC2212_2214 Product data sheet Type Description I ground reference I analog ground reference. This should nominally be the same voltage but should be isolated to minimize noise and error. ...
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... LPC2212/2214 on-chip flash memory. When the CRP is enabled, the JTAG debug port, external memory boot and ISP commands accessing either the on-chip RAM or flash memory are disabled. However, the ISP flash erase command can be executed at any LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers All information provided in this document is subject to legal disclaimers. Rev. 5 — ...
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... In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in “System LPC2212_2214 Product data sheet control”. All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 ...
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... FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. LPC2212_2214 Product data sheet 4.0 GB AHB PERIPHERALS 3 ...
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... I C-bus SPI0 SPI1 and SSP PLL RTC System Control ADC LPC2212_2214 Product data sheet lists the interrupt sources for each peripheral function. Each peripheral device has Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx ...
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... Entire port value can be written in one instruction. • Ports are accessible via either the legacy group of registers (GPIOs) or the group of registers providing accelerated port access (Fast GPIOs). LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers All information provided in this document is subject to legal disclaimers. ...
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... Fractional baud rate generator enables standard baud rates such as 115200 achieved with any crystal frequency above 2 MHz. • Auto-bauding. • Auto-CTS/RTS flow-control fully implemented in hardware. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 LPC2212/2214 © ...
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... Synchronous, Serial, Full Duplex communication. • Combined SPI master and slave. • Maximum data bit rate of 6.12.2 Features available in LPC2212/2214/01 only • Eight to 16 bits per frame. LPC2212_2214 Product data sheet 2 C-bus compliant interface. 2 C-bus may be used for test and diagnostic purposes. 1 ⁄ ...
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... Four external outputs per timer corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 LPC2212/2214 © ...
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... Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. LPC2212_2214 Product data sheet 256 cy(PCLK) 4. All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 ...
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... LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers All information provided in this document is subject to legal disclaimers. ...
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... The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers ...
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... When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers ramp (in the case of power on), the type of crystal DD All information provided in this document is subject to legal disclaimers ...
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... Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. LPC2212_2214 Product data sheet 1 1 ⁄ ...
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... It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2212/2214 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers 1 ⁄ ...
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... Per ground pin. [10] Dependent on package type. [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 series resistor. LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers [1] Conditions ...
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... HIGH-level output current OH I LOW-level output current OL I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers Conditions [2] [ pull- DD(3V3) pull-down ...
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... V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output voltage OL I input leakage current LI LPC2212_2214 Product data sheet …continued Conditions = 1.8 V; DD(1V8) CCLK = 60 MHz C; code T amb while(1){} executed from flash; all peripherals enabled via [11] PCONP register but not ...
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... Only allowed for a short time period. [9] Minimum condition for V = 4.5 V, maximum condition for V I [10] Applies to P1[25:16]. [11] See the LPC2114/2124/2212/2214 User Manual. [12 LPC2212_2214 Product data sheet …continued Conditions is grounded. DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 ...
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... See [7] The absolute voltage error ( the maximum difference between the center of the steps of the actual transfer curve of the T non-calibrated ADC and the ideal transfer curve. See LPC2212_2214 Product data sheet ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2212_2214 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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... Test conditions: Active mode entered executing code from on-chip flash; PCLK = = 25 C; core voltage 1.8 V; all peripherals enabled. T amb Fig 6. Typical LPC2212/01 and LPC2214/01 I LPC2212_2214 Product data sheet all peripherals enabled all peripherals disabled 28 36 measured at different frequencies DD(act) 60 MHz 48 MHz 12 MHz 1 ...
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... Test conditions: Idle mode entered executing code from on-chip flash; PCLK = = 25 C; core voltage 1 amb Fig 8. Typical LPC2212/01 and LPC2214/01 I LPC2212_2214 Product data sheet 60 MHz 48 MHz 12 MHz 1.80 measured at different voltages DD(act) all peripherals enabled all peripherals disabled 28 36 ...
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... I DD(idle) (mA 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 10. Typical LPC2212/01 and LPC2214/01 I LPC2212_2214 Product data sheet 60 MHz 48 MHz 12 MHz 1.80 measured at different voltages DD(idle) 60 MHz 48 MHz 12 MHz 1.80 ...
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... Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 12. Typical LPC2212/01 and LPC2214/01 I LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers 60 MHz 48 MHz 12 MHz 10 35 measured at different temperatures DD(act) 60 MHz 48 MHz ...
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... Fig 13. Typical LPC2212/01 and LPC2214/01 core power-down current I Table 8. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 RTC ADC EMC LPC2212_2214 Product data sheet 10 Typical LPC2212/01 and LPC2214/01 peripheral power consumption in active mode all measurements in amb CCLK = 12 MHz 103 103 9 ...
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... C-bus pins (P0[2] and P0[3]) t fall time f [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Bus capacitance C in pF, from 400 pF. b LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers , V over specified ranges. DD(1V8) DD(3V3) Conditions supplied by an external oscillator (signal generator) ...
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... WELWEH t BLS LOW to BLS HIGH time BLSLBLSH t WE HIGH to address invalid WEHANV time t WE HIGH to data invalid time WEHDNV t BLS HIGH to address invalid BLSHANV time LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers Conditions Min - - - - 5 [1] 5 [1] 5 WST1)) + [2][3] ...
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... Standard read access specifications Access cycle Max frequency standard read f MAX standard write f burst read - initial f burst read - subsequent 3 f [1] See the LPC2114/2124/2212/2214 User Manual for a description of the WSTn bits. LPC2212_2214 Product data sheet Conditions Min (2 cy(CCLK) [1] WST setting WST ...
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... NXP Semiconductors 9.1 Timing XCLK CS addr data t CSLOEL OE Fig 14. External memory read access XCLK CS BLS/WE addr data OE Fig 15. External memory write access LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV ...
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... NXP Semiconductors Fig 16. External clock timing (with an amplitude of at least V LPC2212_2214 Product data sheet Single-chip 16/32-bit ARM microcontrollers t t CHCL CLCX All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 LPC2212/2214 t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) i(RMS) © NXP B.V. 2011. All rights reserved. ...
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... max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT486-1 136E23 Fig 17. Package outline SOT486-1 (LQFP144) LPC2212_2214 Product data sheet ...
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... JTAG PLL POR PWM RAM SPI SRAM SSI SSP TTL UART LPC2212_2214 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Central Processing Unit Debug Communications Channel External Memory Controller First In, First Out General Purpose Input/Output ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 14 June 2011 LPC2212/2214 Single-chip 16/32-bit ARM microcontrollers Change notice Supersedes 201004021F LPC2212_2214 v.4 voltage from typical to minimum. hys 2 C pad hysteresis from 0.5V DD(3V3) - LPC2212_2214 v.3 - LPC2212_2214 v.2 - LPC2212_2214 v © NXP B.V. 2011. All rights reserved. ) DD(pd ...
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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC2212_2214 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 14. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2212_2214 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 14 June 2011 Document identifier: LPC2212_2214 ...