LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 28
LPC2420_60
Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2420_60.pdf
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LPC2420_60
Product data sheet
7.4 Interrupt controller
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be
programmed as FIQ or vectored IRQ types. The programmable assignment scheme
means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs
the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ
latency is achieved when only one request is classified as FIQ, because then the FIQ
Fig 4. LPC2420/2460 memory map
3.75 GB
4.0 GB
3.5 GB
2.0 GB
1.0 GB
0.0 GB
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 22 September 2011
EXTERNAL STATIC AND DYNAMIC MEMORY
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
ON-CHIP STATIC RAM
SPECIAL REGISTERS
AHB PERIPHERALS
APB PERIPHERALS
BOOT ROM
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
002aad316
© NXP B.V. 2011. All rights reserved.
0xFFFF FFFF
0xF000 0000
0xE000 0000
0x8000 0000
0x7FFF FFFF
0x4000 0000
0x3FFF FFFF
0x3FFF 8000
0x0000 0000
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