XA-C3 NXP Semiconductors, XA-C3 Datasheet - Page 18
![The XA-C3 is a member of the Philips XA (eXtended Architecture) family of high-performance 16-bit single-chip microcontrollers](/photos/41/53/415313/sot389-1_3d_sml.gif)
XA-C3
Manufacturer Part Number
XA-C3
Description
The XA-C3 is a member of the Philips XA (eXtended Architecture) family of high-performance 16-bit single-chip microcontrollers
Manufacturer
NXP Semiconductors
Datasheet
1.XA-C3.pdf
(68 pages)
1. SLPEN (Sleep Enable), CANCMR[3], is writable only when the CAN Core is in Normal mode.
Philips Semiconductors
MEMORY-MAPPED REGISTERS
Table 6. Memory-Mapped Registers
Possible Operations: R/W = Read & Write, RO = Read Only, RC = Read then Clear via a service routine, W* = Writable only while the CAN
Core is in Reset mode, x = Undefined after Reset
NOTE:
2000 Jan 25
MnMIDH
MnMIDL
MnMSKH
MnMSKL
MnCTL
MnBLR
MnBSZ
MnFCR
MCPLH
MCPLL
CANINTFLG
MCIR
MEIR
FEENR
FESTR
SPICFG
SPIDATA
SPICS
CANCMR
CANSTR
CANBTR
TxERC
RxERC
EWLR
ECCR
ALCR
GCTL
MIFBTRH
MIFBTRL
MBXSR
XRAMB
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Name
Message n Match ID High
Message n Match ID Low
Message n Mask High
Message n Mask Low
Message n Control
Message n Buffer Location
Message n Buffer Size
Message n Fragmentation Count
Message Complete Status Flags High
Message Complete Status Flags Low
CAN Interrupt Flag Register
Message Complete Information
Message Error Information
Frame Error Enable
Frame Error Status
SPI Configuration
SPI Data
SPI Control and Status
CAN Core Command
CAN Core Status
CAN Core Bus Timing
Tx Error Counter
Rx Error Counter
Error Warning Limit
Error Code Capture
Arbitration Lost Capture
Global Control
MIF Bus Timing Register High
MIF Bus Timing Register Low
Message Buffer and XRAM Segment
Register
XRAM Base Address
Description
CAN/CTL INTERRUPT COMPLETE (CIC) REGISTERS
MESSAGE OBJECT REGISTERS (n = 0 – 31)
MEMORY INTERFACE (MIF) REGISTERS
CAN CORE BLOCK (CCB) REGISTERS
000n
000n
000n
000n
000n
000n
000n
000n
226h
224h
228h
229h
22Ah
22Eh
22Ch
260h
262h
263h
270h
271h
272h
274h
275h
276h
278h
27Ah
27Eh
293h
292h
291h
290h
SPI REGISTERS
4
4
4
4
4
4
4
4
Address Offset
n
n
n
n
n
n
n
n
3
3
3
3
3
3
3
3
n
n
n
n
n
n
n
n
2
2
2
2
2
2
2
2
n
n
n
n
n
n
n
n
1
1
1
1
1
1
1
1
11
n
n
n
n
n
n
n
n
0
0
0
0
0
0
0
0
0000b (n0h)
0010b (n2h)
0100b (n4h)
0110b (n6h)
1000b (n8h)
1010b (nAh)
1100b (nCh)
1110b (nEh)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RC
RC
RC
RO
RO
R/W
RC
R/W
R/W
R/W
R/W*
RO
R/W*
R/W*
R/W*
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
Operation
Word only
Word only
Word only
Word only
Byte
Word only
Byte
Byte
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
ACCESS
Preliminary specification
xxxxh
x x00b
xxxxh
x x000b
00000xxxb
xxxxh
00000xxxb
00xxxxxxb
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
01h (Note 1)
00h
0000h
00h
00h
96h
00h
00h
00h
FFh
EFh
FFh
FEh
Reset Value
XA-C3