XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 22

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 6. Rx DMA modes summary
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is shared
by all eight DMA channels), each DMA channel has seven control
registers and a four-byte Data FIFO. The four Rx DMA channels have
one additional register, the Rx Character Time Out Register. All DMA
registers can be read and written in Memory Mapped Register (MMR)
space. These registers are summarized below.
1999 Sep 24
Periodic Interrupt
Asynchronous
with Character
Time Out
Asynchronous
without interrupt
CMOS 16-bit highly integrated microcontroller
Mode
Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
Byte Count can be calculated by software
from the DMA address pointer.
Byte Count can be calculated by software
from the DMA address pointer.
Byte Count Source
Data FIFO 3
Data FIFO 1
Data FIFO 3
Data FIFO 1
Figure 5. Rx and Tx DMA Registers
Address Pointer
Address Pointer
Buffer Bound
Buffer Bound
Byte Count
Byte Count
When Byte Counter reaches
zero and is reloaded by DMA
hardware from the byte count
register.
If no character is received
within a specified time out
period, then interrupt.
No interrupt generated
DMA Control
FIFO Control
DMA Control
FIFO Control
Data FIFO 2
Data FIFO 0
Rx Time Out
Data FIFO 2
Data FIFO 0
Buffer Base
Buffer Base
Maskable Interrupt
Segment
Segment
22
Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
The DMA channel runs until commanded to
stop by the processor. It generates a
maskable interrupt once per n bytes, where n
is the number written once into the byte count
register by the processor, thus an interrupt is
generated once every n received bytes.
Processor specifies time out period between
incoming characters. If no character is
received within that time, a maskable
interrupt is generated.
Whenever a new character is received, it is
moved into the memory buffer – no interrupt
is generated.
Rx Channel
Tx Channel
SU01240
Description
Preliminary specification
XA-H3