XA-H4 NXP Semiconductors, XA-H4 Datasheet

The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking

XA-H4

Manufacturer Part Number
XA-H4
Description
The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
Manufacturer
NXP Semiconductors
Datasheet
Semiconductors
Preliminary specification
IC28 Data Handbook
hilips
XA-H4
Single-chip 16-bit microcontroller
INTEGRATED CIRCUITS
1999 Sep 24

Related parts for XA-H4

XA-H4 Summary of contents

Page 1

... XA-H4 Single-chip 16-bit microcontroller Preliminary specification IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 1999 Sep 24 ...

Page 2

... Serial ports are USARTs – Synchronous capability Mbps, and include HDLC/SDLC support 1999 Sep 24 The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The XA-H3/H4 devices are members of the Philips XA (eXtended Architecture) family of high performance 16-bit microcontrollers. The XA-H3 and XA-H4 are designed to significantly minimize the need for external components. Dynamic Bus Timing – ...

Page 3

... Philips Semiconductors Single-chip 16-bit microcontroller Table 1. XA-H3 and XA-H4 features comparison Feature Maximum External Memory (Harvard Memory Mode) Maximum External Memory (Unified Memory Mode) Memory Controller supports both Harvard and Unified architectures De-multiplexed Address/Data Bus DRAM Controller DMA Channels Dynamic Bus Sizing Dynamic Bus Timing ...

Page 4

... A17 (A8_A18_A19) 22 A18 23 A19 1999 Sep 24 MOLD MARK XA-H4 Top View 100 Pin LQFP Base Part Number PXAH4 Current Part = PXAH40KFBE MHz – LQFP pkg LQFP Package = SOT407-1 4 Preliminary specification XA-H4 75 P1.7_BRG2_Sync2 74 P1.6_RTS2 73 P1.5_CTS2 72 P1.4_CD2 71 P1.3_TRClk2 70 P1.2_RTClk2 69 P1.1_TxD2 68 P1.0_RxD2 67 P3 ...

Page 5

... Philips Semiconductors Single-chip 16-bit microcontroller LOGIC SYMBOL XA-H4 MISC. Int2 CS4, RAS4 CS5, RAS5 ResetOut, Timer0 Timer1 BRG1, Sync1 Int1 ComClk, TRClk3 BRG3, Sync3 BRG2, Sync2 BRG0, Sync0 1999 Sep Int0 UART1 PORT3 CD1 3.0 RTClk1 3.1 RTS1 3.2 3.3 3.4 CTS1 3.5 RxD1 3.6 TxD1 3.7 TRClk1 UART3 ...

Page 6

... Philips Semiconductors Single-chip 16-bit microcontroller XA-H4 BLOCK DIAGRAM 256 Bytes Data SRAM Port 0 Port 1 Port 2 Port 3 Timer 0 Timer 1 Watchdog Timer DRAM Controller 1999 Sep 24 XA-H4 CPU Core Data MMR Bus SFR Bus Memory Bus Controller 6 Chip Selects Dynamic Bus Sizing Dynamic Bus Timing ...

Page 7

... Philips Semiconductors Single-chip 16-bit microcontroller XA-H4 MEMORY MAPS Code in Dedicated 16 MB Space 1999 Sep 24 FFFFFFh Code and Data Intermixed Throughout 16 MB Space 000000h Unified Memory (also known as von Neuman architecture) FFFFFFh Data in Dedicated 16 MB Space 000000h Harvard Architecture 7 Preliminary specification XA-H4 FFFFFFh 000000h ...

Page 8

... RAS strobes to DRAM. CS1 can be “swapped” with CS0 (see the SWAP operation and control bit in the “Memory Controller” chapter of the XA-H4 User Manual .) CS1 is usually mapped to be based at 000000h after the swap, but is capable of being based anywhere in the 16 MB space. ...

Page 9

... I/O driven low pulse. The duration of this low pulse ranges from 258 system clocks, starting at the time that V When used as GPIO, this pin can be driven low by software without resetting the XA-H4. P3.3_Timer1_BRG1_Sync1: Port 3 Bit 3, or Timer1 input or output, or USART1 BRG output, or P3.3 63 I/O USART1 Sync input or output ...

Page 10

... Base Low and High) registers. Bit Functions and Addresses MSB WARNING – Never write to the BCR register in the XA-H4 – initialized to 07h, the only legal value. This is not the same as for some other XA derivatives. WARNING – Immediately after reset, always write BTRH = 51h, followed by writing BTRL = 40h in that order ...

Page 11

... SWR7 SWR6 SWR5 SWR4 287 286 285 284 283 TF1 TR1 TF0 TR0 IE1 GATE C GATE 11 Preliminary specification XA-H4 Reset Value LSB 222 221 220 – PD IDL 00h 20A 209 208 IM2 IM1 IM0 ...

Page 12

... SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4. 1. The XA-H4 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in the upper byte ...

Page 13

... Read Only USART0 Write Register 0 USART0 Write Register 1 USART0 Write Register 2 USART0 Write Register 3 USART0 Write Register 4 USART0 Write Register 5 USART0 Write Register 6 (XA-H4 only) USART0 Write Register 7 USART0 Write Register 8 USART0 Write Register 9 USART0 Write Register 10 USART0 Write Register 11 USART0 Write Register 12 ...

Page 14

... SDLC byte count low register RO 8 8AEh SDLC byte count high and FIFO status RO 8 8B0h Receive Buffer 8B2h RO 8 8B4h Loop/clock status 8B6-8BEh 14 Preliminary specification XA-H4 Reset Description Value xx f8h 00h 00h 00h xx xx 00h 00h 00h 00h 00h ...

Page 15

... Byte 1 = younger 10Eh = Byte 2 = older, R/W 16 10Eh 10Fh = Byte 3 = younger R/W 8 110h Control Register R/W 8 111h Control & Status Register R/W 8 112h Points data segment 15 Preliminary specification XA-H4 Reset Description Value 00h xx xx 00h 00h 00h 00h 00h xx 00h 00h xx f8h 00h 00h – ...

Page 16

... Current Address pointer A15 – A0 Corresponds to A15 – A0 Byte Count, generates R/W 16 14Ah interrupt if enabled and byte count exceeded. 14C = Byte0 = older R/W 16 14Ch 14D = Byte 1 = younger 16 Preliminary specification XA-H4 Reset Description Value 00h 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h ...

Page 17

... R/W 8 260h GPOut[6-0] are unused, and must be written with zeroes. Autobaud Registers (H4 Only) R/W 8 270h Autobaud echo enable (H4 Only) R/W 8 272h Autobaud Control and Status (H4 Only) 17 Preliminary specification XA-H4 Reset Description Value 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h ...

Page 18

... I/O pin and interrupt. See the XA-G3 data sheet in the IC25 XA Data Handbook for details. Many XA derivatives include a standard XA Timer 2 and standard UARTs. These blocks have been removed in order to provide other functions on the XA-H4. There is no Timer 2 and the UARTs have been replaced with full function USARTs. 18 ...

Page 19

... Because ResetOut does not reflect ResetIn, the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic. This configuration will make all resets (internal or external) appear to the XA as external resets. See the XA-H4 User Manual for a full discussion of the reset functions. ResetIn The ResetIn function is the standard XA-G3 ResetIn function ...

Page 20

... For the following discussion, see Figure 3. WARNING: On the external bus, ALL XA-H4 reads are 16-bit Reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus 8-bit bus, this will appear as two consecutive 8-bit reads even though the CPU instruction specified a byte read ...

Page 21

... Byte Reads, both BLE and BHE will go active.During DRAM cycles only, the appropriate CAS Address will be multiplexed onto pins A17 – A7 after the assertion of RAS and prior to the assertion of BHE (CASH) and BLE (CASL.) See AC timing diagrams and the XA-H4 User Manual for complete details. 1999 Sep 24 ClkOut to be output enabled at reset, but it may be turned off (tri-state disabled) by software via the MICFG MMR ...

Page 22

... Description This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the base address for the 4 kB Memory Mapped Register space. See the XA-H4 User Manual for using this SFR to relocate the MMRs. Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped Register space ...

Page 23

... DMA address Match pointer. 1999 Sep 24 summarized in Table 6. For full details on implementation and use, see the XA-H4 User Manual . Maskable Interrupt At end of received packet When a complete or aborted SDLC/HDLC packet has been received, the packet byte count and status information are stored in memory with the packet. A maskable interrupt is generated ...

Page 24

... DMA into memory of received data. Thus, once the baud rate is determined, reception begins without intervention from the processor. When the baud rate is detected, a maskable interrupt is sent to the processor. See the “Autobaud” chapter in the XA-H4 User Manual for details. I/O Port Output Configuration ...

Page 25

... HSWR 3–0 1999 Sep 24 See the IC25 XA Data Handbook for a full explanation of the exception structure, including event interrupts, of the XA CPU. Because the High Priority Software Interrupts are not implemented on all XA derivitives, they are explained in the XA-H4 User Manual . DMAH DMAL Interrupt Enable/ ...

Page 26

... Table 7. USART0 Interrupts (Interrupt structure is the same, except for bit locations, for all 4 USARTs) Potential Individual Enable Bit USART0 Interrupt MMR Hex Offset Rx Character Available – SDLC EOF – (XA-H4 Only) CRC/Framing Error – Rx Overrun – Parity Error WR1[2] 802[2] Tx Buffer Empty See WR1[1] ...

Page 27

... EX0 426[0] 330 Vector Address 0100–0103 0104–0107 0108–010B 010C–010F 0110–0113 0114–0117 0118–011B 27 Preliminary specification XA-H4 Priority Register Bit Arb. Rank Field (SFR) PHSWR3 17 4A7[6:4] PHSWR2 16 4A7[2:0] PHSWR1 15 4A6[6:4] PHSWR0 14 4A6[2:0] PSC23 ...

Page 28

... 5 3 must be externally limited as follows (NOTE: This is +85 C specification for Preliminary specification XA-H4 Rating Unit –55 to +125 C –65 to +150 C –0 +0 1.5 W Limits Unit Unit Min Typ Max 64 ...

Page 29

... See notes after the 3 Timing Table 1999 Sep 24 Parameter Parameter All Cycles All DRAM Cycles 8 Generic Data Read Only Data Read and Instruction Fetch Cycles 2 Write Cycles Refresh Wait Input 29 Preliminary specification XA-H4 Limits Unit Unit Min Max 0 30 MHz 33.33 – 0.5 – 0.4 – ...

Page 30

... ClkOut pF. 6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H4 User Manual for details. 7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from bytes long 16-bit bus, A3 – ...

Page 31

... Figure 7. Generic (SRAM, ROM, Flash, I/O Devices, etc.) Read on 16-Bit Bus 1999 Sep 24 is programmable, and is represented the – 16= ((2 * 33.33) – 16) = 50.6 ns. As the system clock C becomes greater CHAH t t CHSL AHDR t CHSH t (Note 2) DIH t DIS 31 Preliminary specification XA-H4 RP (Does Not Include A0) SU01277 ...

Page 32

... CHDV D 1999 Sep CHAV Address + DIH DIH Note 2 Note DIS DIS t CHSH t CHSL t SHAH Note 1 t SHDH Figure 9. Generic (SRAM, I/O Devices, etc.) Write 32 Preliminary specification XA-H4 CHAV Address + 4 t CHSH t OHDE t DIH (Note 2) t DIS Driven by XA SU01131 SU01278 ...

Page 33

... Figure 10. DRAM Single Read Cycle t CHAV t t CHAH CHAH CAS ADDRESS CAS ADDRESS +2 t CHAV t CHSH t CHSL t t CPWH t AVSL Note 4 t DIS Word (from CAS Addr) 33 Preliminary specification XA-H4 t CHSH t OHDE t DIH Note 2 SU01279 t CHSH CPWL t OHDE t DIS Note 4 Word (from CAS Addr +2) SU01280 ...

Page 34

... Figure 13. DRAM Write (on 16-Bit Bus, also 8-Bit Write on 8-Bit Bus) 1999 Sep 24 t CHSL t CHAV CAS ADDRESS t CHAH t CHSH t AVSL t Note 2 DIS INSTRUCTION t CHSL CAS ADDRESS Note 1 t AVSL Valid Data 34 Preliminary specification XA-H4 t CHAV CAS ADDRESS +2 t CHAH t CHSH t CPWH Note 2 t DIS INSTRUCTION SU01281 t CHAH t CHSH t CHSH SU01282 ...

Page 35

... Note: On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus 8-bit bus, this will appear as two consecutive 8-bit reads even though the CPU will only use one of the two bytes ...

Page 36

... Sep 24 t SHAH t AVSL t t SHDH DVSL Figure 16. Generic 16-Bit Write on 8-Bit Bus t t CHSL CHAV CAS ADDRESS EVEN t CHAH t AVSL t DIS LS Byte 36 Preliminary specification XA-H4 t CHSH t SHAH SU01246 t CHAV CAS ADDRESS ODD t CHAH t CHSH t CHSH t CPWH Note Note 2 DIS DIH MS Byte ...

Page 37

... DIH LS Byte MS Byte LS Byte CAS ADDR CAS ADDR ODD EVEN t CHSH t CHSL t CPWL t CPWH Note 4 t DIS LS Byte MS Byte 37 Preliminary specification XA- CAS ADDR ODD t CHSH t CHSH t OHDE t Note 2 DIH MS Byte SU01285 CAS ADDR ODD t CHSH t ...

Page 38

... CLRL CASH, CASL RAS and CAS terminate together. The active low portion of RAS can be programmed to last from clock cycles. The high portion of RAS after Refresh can be programmed to last from clock cycles. See Chapter 3 of the XA-H4 User Manual. RAS NOTE: ...

Page 39

... Setup time of WAIT to rising edge of ClkOut – Hold time of WAIT after ClkOut High. WH 1999 Sep 24 0 – 0 CHCL CLCX t C Figure 23. External Clock Input Drive t CODH Figure 24. ClkOut Duty Cycle Figure 25. External WAIT Pin Timing 39 Preliminary specification XA-H4 t CHCX t CLCH SU01146 SU01147 SU01148 ...

Page 40

... Philips Semiconductors Single-chip 16-bit microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 1.4 mm 1999 Sep 24 40 Preliminary specification XA-H4 SOT407-1 ...

Page 41

... Philips Semiconductors Single-chip 16-bit microcontroller 1999 Sep 24 NOTES 41 Preliminary specification XA-H4 ...

Page 42

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 1999 Sep 24 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 42 Preliminary specification XA-H4 All rights reserved. Printed in U.S.A. Date of release: 09-99 9397 750 06432 ...

Related keywords