EM773FHN33 NXP Semiconductors, EM773FHN33 Datasheet
EM773FHN33
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EM773FHN33 Summary of contents
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EM773 Energy metering IC flash and 8 kB SRAM Rev. 2 — 3 January 2012 1. General description The EM773 is an ARM Cortex-M0 based, low-cost 32-bit energy metering IC, designed for 8/16-bit smart metering applications. ...
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... NXP Semiconductors Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. One SPI controller with SSP features and with FIFO and multi-protocol capabilities. I data rate of 1 Mbit/s with multiple address recognition and monitor mode. ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name EM773FHN33 HVQFN33 EM773 Product data sheet Description HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 January 2012 ...
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... NXP Semiconductors 5. Block diagram EM773 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD DTR, CTS, RTS CT32B0_MAT[2:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 32-bit COUNTER/TIMER 1 CT32B1_MAT[3:0] CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 Fig 1. EM773 block diagram EM773 Product data sheet SWD TEST/DEBUG INTERFACE ARM CORTEX-M0 FLASH 32 kB ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration HVQFN 33 package EM773 Product data sheet terminal 1 index area XTALIN 4 XTALOUT PIO1_8 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 January 2012 ...
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... NXP Semiconductors 6.2 Pin description Table 2. EM773 pin description table Symbol Pin PIO0_0 to PIO0_10 [2] RESET/PIO0_0 2 [3] PIO0_1/CLKOUT/ 3 CT32B0_MAT2 [3] PIO0_2/SSEL0/ 8 CT16B0_CAP0 [3] PIO0_3 9 [4] PIO0_4/SCL 10 [4] PIO0_5/SDA 11 [3] PIO0_6/SCK0 15 [3] PIO0_7/CTS 16 [3] PIO0_8/MISO0/ 17 CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 CT16B0_MAT1 EM773 Product data sheet Start Type Reset Description ...
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... NXP Semiconductors Table 2. EM773 pin description table Symbol Pin [3] SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 [5] I_HIGHGAIN 21 PIO1_1 to PIO1_9; PIO1_11 [5] VOLTAGE 22 [5] R/PIO1_1/ 23 CT32B1_MAT0 [5] R/PIO1_2/ 24 CT32B1_MAT1 [5] SWDIO/PIO1_3/ 25 CT32B1_MAT2 PIO1_4/ 26 CT32B1_MAT3/WAKEUP [3] PIO1_5/RTS/ 30 CT32B0_CAP0 [3] PIO1_6/RXD/ 31 CT32B0_MAT0 [3] PIO1_7/TXD/ 32 CT32B0_MAT1 [3] PIO1_8 7 [3] PIO1_9 12 I_LOWGAIN 20 EM773 Product data sheet …continued Start ...
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... NXP Semiconductors Table 2. EM773 pin description table Symbol Pin PIO1_11 27 PIO2_0 [3] PIO2_0/DTR 1 PIO3_0 to PIO3_5 [3] PIO3_2 28 [3] PIO3_4 13 [3] PIO3_5 [6] XTALIN 4 [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled; (pins pulled up to full V no pull-up/down enabled ...
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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The EM773 contains on-chip flash memory. 7.3 On-chip SRAM The EM773 contains a total on-chip static RAM memory. ...
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... NXP Semiconductors EM773 4 GB reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM reserved 32 kB on-chip flash 0 GB Fig 3. EM773 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...
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... NXP Semiconductors 7.8 UART The EM773 contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. ...
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... NXP Semiconductors receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. 7.10.1 Features • The C-bus interface also supports Fast-mode Plus with bit rates Mbit/s. ...
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... NXP Semiconductors • Counter or timer operation. • One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. ...
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... NXP Semiconductors 7.15 Clocking and power control 7.15.1 Crystal oscillators The EM773 includes three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the EM773 will operate from the Internal RC oscillator until switched by software ...
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... NXP Semiconductors 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency the maximum CPU operating frequency, by the system PLL ...
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... NXP Semiconductors 7.15.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the EM773 for one of the following power modes: • Default mode corresponding to power configuration after reset. ...
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... NXP Semiconductors 7.16 System control 7.16.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down ...
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... NXP Semiconductors 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too the user’ ...
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... NXP Semiconductors 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) Power consumption in low-current mode I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output ...
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... NXP Semiconductors Table 4. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) I LOW-level input current V ...
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... NXP Semiconductors Table 4. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter I LOW-level output OL current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage ...
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... NXP Semiconductors Table 4. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [ C. ...
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... NXP Semiconductors 9.1 BOD static characteristics Table C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see EM773 user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see EM773 user manual): • ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 5. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. EM773 Product data sheet ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 7. EM773 Product data sheet −40 −15 Conditions 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled ...
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... NXP Semiconductors (μA) Fig 8. (μA) Fig 9. EM773 Product data sheet 5 4.5 3 3 2.5 1.5 −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Deep-sleep mode: Typical supply current I supply voltages 0.6 0.4 0.2 0 −40 −15 ...
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... NXP Semiconductors 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements ...
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... NXP Semiconductors 9.4 Electrical pin characteristics V Fig 10. High-drive output: Typical HIGH-level output voltage V (mA) Fig 11. I EM773 Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5. ...
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... NXP Semiconductors (mA) Fig 12. Typical LOW-level output current I V Fig 13. Typical HIGH-level output voltage V EM773 Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) Fig 14. Typical pull-up current I (μA) Fig 15. Typical pull-down current I EM773 Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 °C ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 7. = 40 C to +85 C. T amb Symbol Parameter wait V I [1] See [2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. Fig 16. Power-up ramp 10.2 Flash memory Table 8. ...
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... NXP Semiconductors 10.3 External clock Table 9. = 40 C to +85 amb Symbol f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors 10.4 Internal oscillators Table 10. = 40 C to +85 C; 2.7 V amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. (MHz) Fig 18. Internal RC oscillator frequency versus temperature Table 11 ...
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... NXP Semiconductors 10.5 I/O pins Table 12. = 40 C to +85 C; 3.0 V amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.6 I C-bus Table 13. = 40 C to +85 C. T amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors [6] The maximum t output stage t SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. ...
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... NXP Semiconductors Table 14. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI slave (in SPI mode) T PCLK cycle time cy(PCLK) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode h(Q) = (SSPCLKDIV SCR) CPSDVSR ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 21. SPI slave timing in SPI mode EM773 Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 January 2012 ...
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... NXP Semiconductors 11. Application information 11.1 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...
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... NXP Semiconductors Fig 23. Oscillator modes and models: oscillation mode of operation and external crystal Table 15. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 16. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.2 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.3 Standard I/O pad configuration Figure 24 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.4 Reset pad configuration Fig 25. Reset pad configuration 11.5 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown in Table 17 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level Input clock: crystal oscillator (12 MHz) ...
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... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (mm are the original dimensions) (1) (1) Unit max 0.05 0.30 mm nom 0.85 0.2 min 0.00 0.18 Note 1 ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 28. Reflow soldering of the HVQFN33 package EM773 Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7.95 CU ...
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... NXP Semiconductors 14. Abbreviations Table 18. Acronym AHB APB BOD GPIO PLL RC SPI SSI SSP TEM UART EM773 Product data sheet Abbreviations Description Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface Serial Synchronous Interface ...
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... NXP Semiconductors 15. Revision history Table 19. Revision history Document ID EM773 v.2 Modifications: EM773 v.1 EM773 Product data sheet Release date Data sheet status 20120103 Product data sheet • Updated Section 7.7.1 “Features”. • Updated Section 7.14 “Windowed WatchDog • Updated Section 7.15.2 “System • Added Section 7.15.5.1 “Power • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 9 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 9 7.2 On-chip flash program memory . . . . . . . . . . . . 9 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.4 Memory map 7.5 Nested Vectored Interrupt Controller (NVIC ...