BSP225 NXP Semiconductors, BSP225 Datasheet - Page 3

Intermediate level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using vertical D-MOS technology

BSP225

Manufacturer Part Number
BSP225
Description
Intermediate level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using vertical D-MOS technology
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain lead minimum 6 cm
THERMAL RESISTANCE
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain lead minimum 6 cm
April 1995
P
T
T
R
SYMBOL
SYMBOL
V
V
I
I
stg
j
tot
th j-a
P-channel enhancement mode vertical
D-MOS transistor
D
DM
DS
GSO
from junction to ambient (note 1)
drain-source voltage
gate-source voltage
drain current
drain current
total power dissipation
storage temperature range
junction temperature
PARAMETER
PARAMETER
3
open drain
DC value
peak value
up to T
amb
CONDITIONS
= 25 C (note 1)
83.3
MIN.
65
VALUE
Product specification
250
20
225
600
1.5
150
150
BSP225
MAX.
K/W
UNIT
V
V
mA
mA
W
UNIT
C
C
2
2
.
.

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