EP2AGX260EF29I5 Altera Corporation, EP2AGX260EF29I5 Datasheet - Page 35

• Manufacturer Part Number: EP2AGX260EF29I5
• Description: IC ARRIA II GX FPGA 260K 780FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX260EF29I5

• Number Of Logic Elements/cells: 244188
• Number Of Labs/clbs: 10260
• Total Ram Bits: 12038144
• Number Of I /o: 372
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-BBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

Table 1–34. Transceiver Specifications for Arria II GX Devices
Digital reset
pulse width
Notes to
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The rise/fall time is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is
(5) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX V
(8) The rate matcher supports only up to ±300 parts per million (ppm).
(9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(10) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to
(11) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(12) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
Description
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to
you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum
specification listed.
Symbol/
Table
1–34:
Condition
—
ICM
setting if the input serial data standard is LVDS and the link is DC-coupled.
Min
I3
Typ
Max
(Note 1)
Min
(Part 7 of 7)
Figure
Typ
AN 558: Implementing Dynamic Reconfiguration in Arria II
1–1.
C4
Minimum is 2 parallel clock cycles
Max
Figure
Figure
1–1.
1–2.
Min
C5 and I5
Typ
Max
Devices.
Min
Figure
Typ
C6
1–1.
Max
Unit