EP2AGX260EF29I5 Altera Corporation, EP2AGX260EF29I5 Datasheet - Page 40

• Manufacturer Part Number: EP2AGX260EF29I5
• Description: IC ARRIA II GX FPGA 260K 780FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX260EF29I5

• Number Of Logic Elements/cells: 244188
• Number Of Labs/clbs: 10260
• Total Ram Bits: 12038144
• Number Of I /o: 372
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-BBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–32
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 5 of 5)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
-3 dB Bandwidth
Transceiver-FPGA Fabric Interface
Interface speed
Digital reset pulse width
Notes to
(1) The 3x speed grade is the fastest speed grade offered in the following Arria II GZ devices: EP2AGZ225, EP2AGZ300, and EP2AGZ350.
(2) The rise and fall time transition is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
(5) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx)
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX V
(8) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
(9) The rate matcher supports only up to
(10) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(11) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in
(12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(13) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(14) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the
(15) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode.
channels physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig
instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
manual mode. Refer to
Clocking for Arria II Devices
Description
Table
Symbol/
1–35:
Figure 1–1 on page
chapter.
ICM
SRIO 3.125 Gbps
(OIF) CEI PHY at
(OIF) CEI PHY at
setting if the input serial data standard is LVDS.
SRIO 1.25 Gbps
SRIO 2.5 Gbps
SONET OC12
SONET OC48
4.976 Gbps
6.375 Gbps
Conditions
PCIe Gen1
PCIe Gen2
±
XAUI
GIGE
300 ppm.
—
—
1–33.
Min
25
–C3 and –I3
Typ
Minimum is two parallel clock cycles
—
(1)
Max
325
2.5 - 3.5
2.5 - 4.5
1.5 - 2.5
Figure 1–1 on page
3 - 5.5
3 - 5.5
3.5 - 6
7 - 11
5 - 10
6 - 8
2 - 4
2 - 4
Chapter 1: Device Datasheet for Arria II Devices
Min
25
Figure 1–1 on page
Figure 1–2 on page
–C4 and –I4
December 2011 Altera Corporation
1–33.
Typ
—
Switching Characteristics
Max
250
1–33.
1–33.
Transceiver
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
—