EP4S100G5H40I3N Altera Corporation, EP4S100G5H40I3N Datasheet

Page 1

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...

Page 2

... Pinouts for Stratix IV E devices designed to allow migration of designs from ■ Stratix III to Stratix IV E with minimal PCB impact Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Feature Summary IP Compiler for PCI Express User Guide. June 2011 Altera Corporation ...

Page 3

... Architecture in Stratix IV Devices Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. June 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

Page 4

... LVDS interface with DPA and Soft-CDR and Soft-CDR Feature Summary General Purpose I/O and Memory Interface PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL General Purpose I/O and Memory Interface June 2011 Altera Corporation ...

Page 5

... Figure 1–3 shows a high-level Stratix IV GT chip view. Figure 1–3. Stratix IV GT Chip View Note to Figure 1–3: (1) Resource counts vary with device selection, package selection, or both. June 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory I/O and Memory ...

Page 6

... Transaction layer support for up to two virtual channels (VCs) ■ Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features PCI Express Compiler User Guide. June 2011 Altera Corporation ...

Page 7

... On-package and on-chip power supply decoupling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors ■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors June 2011 Altera Corporation PCI Express Compiler User Guide. Stratix IV Device Handbook Volume 1 1–7 ...

Page 8

... (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in ■ Stratix IV GX and Stratix IV GT devices ■ (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in Stratix IV E devices Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features June 2011 Altera Corporation ...

Page 9

... Programmable DQ group widths bits (includes parity bits) ■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate register capabilities provide a robust external memory interface solution June 2011 Altera Corporation ) and on-chip parallel (R ) termination with auto-calibration for termination for differential I/Os D ratio of 8:1:1 to reduce loop inductance in the package— ...

Page 10

... I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines Stratix IV GT Device Family Pin Connection Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features and the Guidelines. June 2011 Altera Corporation ...

Page 11

Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option ALMs 29,040 42,240 70,300 LEs 72,600 105,600 175,750 0.6 Gbps- 8.5 Gbps Transceivers — ...

Page 12

Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option M9K Blocks 462 660 (256 x 36 bits) M144K Blocks 16 16 (2048 x 72 bits) Total Memory (MLAB+M9K 7,370 9,564 13,627 +M144K) ...

Page 13

Table 1–2 lists the Stratix IV GX device package options. Table 1–2. Stratix IV GX Device Package Options F780 Device ( mm) (5) EP4SGX70 DF29 — EP4SGX110 DF29 — EP4SGX180 DF29 — EP4SGX230 DF29 — EP4SGX290 — ...

Page 14

Table 1–3 lists the Stratix IV GX device on-package decoupling information. Table 1–3. Stratix IV GX Device On-Package Decoupling Information Ordering Information V CC EP4SGX70 HF35 21uF + 2470nF EP4SGX110 HF35 21uF + 2470nF HF35 EP4SGX180 21uF + 2470nF KF40 ...

Page 15

... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (2) Four multiplier adder mode. (3) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (4) This data is preliminary. June 2011 Altera Corporation EP4SE360 EP4SE530 780 1152 ...

Page 16

... Architecture Features F1760 (6) (42 42.5 mm) (6) — — — — (3) F43 (3) F43 Package V CCIO 10 nF per bank 10 nF per bank 10 nF per bank EP4S100G4 EP4S100G5 1932 1517 1932 141,440 212,480 353,600 531,200 June 2011 Altera Corporation ...

Page 17

... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (5) This data is preliminary. June 2011 Altera Corporation EP4S40G5 EP4S100G2 EP4S100G3 ...

Page 18

... H40 (4), (5) Sheet. (Note CCIO CCL_GXB CCA_L/R 100 nF per (2) 100 nF transceiver block 100 nF per (2) 100 nF transceiver block Architecture Features 1932 Pin ( mm) — — — F45 F45 F45 V V CCT_L/R CCR_L/R 100 nF 100 nF 100 nF 100 nF June 2011 Altera Corporation ...

Page 19

... D: 8 230 F: 16 290 H: 24 360 K: 36 530 N: 48 820 Package Type F: FineLine BGA (FBGA) H: Hybrid FineLine BGA June 2011 Altera Corporation Ball Array Dimension Corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins 1– ...

Page 20

... Table 1–8. Ordering Information Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 1 being the fastest Operating Temperature C: Commercial temperature ( Industrial temperature (t = 0°C to 100° June 2011 Altera Corporation ...

Page 21

... Updated Table 1–2. ■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT ■ Device.” on page 1–15. July 2008 1.1 Revised “Introduction”. May 2008 1.0 Initial release. June 2011 Altera Corporation Changes Stratix IV Device Handbook Volume 1 1–21 ...

Page 22

... Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Ordering Information June 2011 Altera Corporation ...