STM32W108CB STMicroelectronics, STM32W108CB Datasheet - Page 151

• Manufacturer Part Number: STM32W108CB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
10.2
10.3
10.3.1
Table 88.
31
15
30
14
Interrupts
Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority.
Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and
writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it.
on page 186
Several kinds of timer events can generate a timer interrupt, and each has a status flag in
the INT_TIMxFLAG register to identify the reason(s) for the interrupt:
●
●
●
Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture
mode, reading the TIMx_CCRy register will also clear the INT_TIMCCRyIF bit.
The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request
an ARM® Cortex-M3 timer interrupt. Only the events whose bits are set to 1 in
INT_TIMxCFG can do so.
If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already
set, the corresponding capture/compare missed flag is set in the INT_TMRxMISS register.
Clear a bit in the INT_TMRxMISS register by writing a 1 to it.
General-purpose timer (1 and 2) registers
Timer x control register 1 (TIMx_CR1)
Address offset: 0xE000 (TIM1) and 0xF000 (TIM2)
Reset value:
Timer x control register 1 (TIMx_CR1)
Bit 7 TIM_ARBE: Auto-Reload Buffer Enable
29
13
INT_TIMTIF - set by a rising edge on an external trigger, either edge in gated mode
INT_TIMCCRyIF -set by a channel y input capture or output compare event
INT_TIMUIF - set by an update event
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
28
12
Reserved
describes the interrupt system in detail.
27
11
0x0000 0000
26
10
25
9
Doc ID 16252 Rev 13
24
8
Reserved
TIM_A
RBE
23
rw
7
22
6
TIM_CMS
rw
21
5
TIM_D
20
rw
IR
4
General-purpose timers
TIM_O
PM
19
rw
3
Section 12: Interrupts
TIM_U
RS
18
rw
2
TIM_U
DIS
17
rw
1
151/232
TIM_C
EN
16
rw
0