STM32W108CB STMicroelectronics, STM32W108CB Datasheet - Page 177

• Manufacturer Part Number: STM32W108CB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Note:
11.1.7
Sample time
ADC sample time is programmed by selecting the sampling clock and the clocks per
sample.
●
●
Table 110
results.
Table 110. ADC sample times
ADC sample timing is the same whether the STM32W108 is using the 24 MHz crystal
oscillator or the 12 MHz high-speed RC oscillator. This facilitates using the ADC soon after
the CPU wakes from deep sleep, before switching to the crystal oscillator.
Operation
Setting the ADC_EN bit in the ADC_CFG register enables the ADC; once enabled, it
performs conversions continuously until it is disabled. If the ADC had previously been
disabled, a 21 µs analog startup delay is imposed before the ADC starts conversions. The
delay timing is performed in hardware and is simply added to the time until the first
conversion result is output.
When the ADC is first enabled, and or if any change is made to ADC_CFG after it is
enabled, the time until a result is output is double the normal sample time. This is because
the ADC’s internal design requires it to discard the first conversion after startup or a
configuration change. This is done automatically and is hidden from software except for the
longer timing. Switching the processor clock between the RC and crystal oscillator also
causes the ADC to go through this startup cycle. If the ADC was newly enabled, the analog
delay time is added to the doubled sample time.
ADC_PERIOD
The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the
ADC_CFG register is clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is
selected. The 6 MHz sample clock offers faster conversion times but the ADC
resolution is lower than that achieved with the 1 MHz clock.
The number of clocks per sample is determined by the ADC_PERIOD bits in the
ADC_CFG register. ADC_PERIOD values select from 32 to 4096 sampling clocks in
powers of two. Longer sample times produce more significant bits. Regardless of the
sample time, converted samples are always 16-bits in size with the significant bits left-
aligned within the value.
0
1
2
3
4
5
6
7
shows the options for ADC sample times and the significant bits in the conversion
Sample
clocks
1024
2048
4096
128
256
512
32
64
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock
1024
2048
4096
128
256
512
Sample time (µs)
32
64
Doc ID 16252 Rev 13
5.33
10.7
21.3
42.7
85.3
170
341
682
Sample frequency (kHz)
0.977
0.488
0.244
31.3
15.6
7.81
3.91
1.95
Analog-to-digital converter
93.8
46.9
23.4
11.7
5.86
2.93
1.47
188
Significant
bits
10
11
12
5
6
7
8
9
177/232