STM32W108HB STMicroelectronics, STM32W108HB Datasheet - Page 98

• Manufacturer Part Number: STM32W108HB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108HB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
9.9.2
Table 57.
98/232
31
15
30
14
SPI configuration register (SCx_SPICFG)
Address offset: 0xC858 (SC1_SPICFG) and 0xC058 (SC2_SPICFG)
Reset value:
SPI configuration register (SCx_SPICFG)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
29
13
SC_SPIRXDRV: Receiver-driven mode selection bit (SPI master mode only). Clear this bit to
initiate transactions when transmit data is available. Set this bit to initiate transactions when the
receive buffer (FIFO or DMA) has space.
SC_SPIMST: Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave
mode.
SC_SPIRPT: This bit controls behavior on a transmit buffer underrun condition in slave mode.
Clear this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to
this bit take effect when the transmit FIFO is empty and the transmit serializer is idle.
SC_SPIORD: This bit specifies the bit order in which SPI data is transmitted and received.
0: Most significant bit first.
SC_SPIPHA: Clock phase configuration: clear this bit to sample on the leading (first edge) and
set this bit to sample on the second edge.
SC_SPIPOL: Clock polarity configuration: clear this bit for a rising leading edge and set this bit
for a falling leading edge.
28
12
27
11
Reserved
0x0000 0000
26
10
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
25
9
Doc ID 16252 Rev 13
24
8
Reserved
23
7
22
6
1: Least significant bit first.
SC_SPI
RXDRV
21
rw
5
SC_S
PIMS
20
rw
T
4
SC_SP
IRPT
19
rw
3
SC_SP
IORD
18
rw
2
SC_SP
IPHA
17
rw
1
SC_SP
IPOL
16
rw
0