STM8L151G4 STMicroelectronics, STM8L151G4 Datasheet - Page 7
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STM8L151G4
Manufacturer Part Number
STM8L151G4
Description
8-bit ultra-low-power MCU, up to 32 KB Flash, 1 KB Data EEPROM
Manufacturer
STMicroelectronics
Datasheet
1.STM8L151G4.pdf
(126 pages)
Specifications of STM8L151G4
Temp. Range
- 40 °C to 85, 105 or 125 °C
5 Low Power Modes
Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with full RTC (1.3 μA), Halt (350 nA)
Consumption
195 μA/MHz+440μA
Ultralow Leakage Per I/0
50 nA
Fast Wakeup From Halt
4.7 μs
Lcd
up to 4x28 segments w/ step-up converter
4 Channels; Supported Peripherals
ADC, DAC, SPI, I2C, USART, timers
2 Watchdogs
1 Window, 1 Independent
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8L151G4U3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STM8L151G4U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8L151G4U6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
STM8L151G4U6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8L151G4U6TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8L151G4Y6TR
Manufacturer:
ST
Quantity:
20 000
STM8L151xx, STM8L152xx
List of figures
Figure 1.
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Figure 47.
Medium density STM8L15x device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Medium density STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM8L151Cx 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151Kx 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151Gx UFQFPN28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151Gx WLCSP28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L152Cx 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L152Kx 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical HSI frequency vs V
Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical pull-up resistance R
Typical pull-up current I
Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical NRST pull-up resistance R
Typical NRST pull-up current I
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI1 timing diagram - slave mode and CPHA=1
SPI1 timing diagram - master mode
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum dynamic current consumption on V
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Power supply and reference decoupling (V
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 107
LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Recommended 7 x 7 mm UFQFPN48 footprint (dimensions in mm) . . . . . . . . . . . . . . . . 114
LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
pu
vs V
DD
PU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Doc ID 15962 Rev 9
pu
DD
vs V
vs V
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PU
DD
(1)
DD
vs V
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DD
REF+
REF+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
not connected to V
(1)
supply pin during ADC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DDA
). . . . . . . . . . . . . 107
List of figures
7/126