STM8AF6248 STMicroelectronics, STM8AF6248 Datasheet - Page 72

no-image

STM8AF6248

Manufacturer Part Number
STM8AF6248
Description
STM8AF62 Standard Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF6248

Max Fcpu
16 MHz
Flash Program Memory
16 to 32 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
Data Memory
0.5 to 1 Kbyte true data EEPROM; endurance 300 kcycles
Ram
1 to 2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM8AF6248
Manufacturer:
ST
0
Part Number:
STM8AF6248TA
Manufacturer:
st
Quantity:
108
Part Number:
STM8AF6248TA
Manufacturer:
ST
0
Part Number:
STM8AF6248TA/C
Manufacturer:
ST
0
Part Number:
STM8AF6248TAY
Manufacturer:
STMicroelectronics
Quantity:
50
Part Number:
STM8AF6248TAY
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8AF6248TAY
Manufacturer:
ST
0
Part Number:
STM8AF6248TAY
0
Part Number:
STM8AF6248TC
Manufacturer:
ST
Quantity:
2 072
Part Number:
STM8AF6248TCY
Manufacturer:
STMicroelectronics
Quantity:
50
Part Number:
STM8AF6248TD
Manufacturer:
ST
Quantity:
284
Electrical characteristics
10.3.10
72/91
I
Table 41.
1. f
2. Data based on standard I
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
t
t
t
t
t
t
t
t
t
t
t
t
C
2
w(SCLL)
w(SCLH)
su(SDA)
h(SDA)
r(SDA)
r(SCL)
f(SDA)
f(SCL)
h(STA)
su(STA)
su(STO)
w(STO:STA)
Symbol
C interface characteristics
b
time
undefined region of the falling edge of SCL
MASTER
, must be at least 8 MHz to achieve max fast I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
(V
SDA and SCL fall time
(V
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
I
2
DD
DD
C characteristics
= 3 to 5.5 V)
= 3 to 5.5 V)
2
C protocol requirement, not tested in production
Parameter
Doc ID 14952 Rev 5
2
C speed (400 kHz)
Standard mode I
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
-
-
-
(2)
Max
1000
300
400
STM8AF61xx, STM8AF62xx
-
-
-
-
-
-
-
-
(2)
2
C Fast mode I
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
-
-
-
(2)
Max
900
300
300
400
2
C
-
-
-
-
-
-
-
(3)
(2)
(1)
Unit
pF
µs
ns
µs
µs
µs

Related parts for STM8AF6248