ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 99
ST7263BH2
Manufacturer Part Number
ST7263BH2
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST7263BH6.pdf
(186 pages)
Specifications of ST7263BH2
4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection
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ST7263Bxx
Interrupt/DMA register (IDR)
Reset value: xxxx 0000 (x0h)
Figure 45. DMA buffers
DA7
7
[7:6] DA[7:6] DMA address bits 7-6.
[5:4] EP[1:0] Endpoint number (read-only). These bits identify the endpoint which
[3:0] CNT[3:0] Byte count (read only).
DA15-6,000000
DA6
Software must reset these bits. See the description of the DMAR register and
Figure
required attention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR) the software should read the EP
bits to identify the endpoint which has sent or received a packet.
This field shows how many data bytes have been received during the last data
reception.
Note: Not valid for data transmission.
45.
EP1
Doc ID 7516 Rev 8
EP0
101111
101000
100111
100000
011111
011000
010111
010000
001111
001000
000111
000000
Read.write
CNT3
Endpoint 2 RX
Endpoint 1 RX
Endpoint 0 RX
Endpoint 2 TX
Endpoint 1 TX
Endpoint 0 TX
CNT2
On-chip peripherals
CNT1
CNT0
0
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