ST7263-EMU2 STMicroelectronics, ST7263-EMU2 Datasheet
ST7263-EMU2
Specifications of ST7263-EMU2
Related parts for ST7263-EMU2
ST7263-EMU2 Summary of contents
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... SCI, ADC, USB 4.0V to 5.5V 8 Mhz (with 24 MHz oscillator MHz (with 12 MHz oscillator) 0°C to +70°C SO34/SDIP32 1 ST72E631 (CSDIP32W) ST7263 & I DATASHEET PSDIP32 CSDIP32W SO34 (Shrink) assembler, linker, C-compiler, hardware emulator, programming ST72632 ST72633 8K 4K 256 (64) Watchdog, 16-bit timer, ADC, USB Rev. 1 1/109 1 ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST7263 7.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4 POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 98 7.7 CONTROL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.1 USB - Universal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.9 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 PACKAGE CHARACTERISTICS ...
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... I2C Multi Master interface (not on all prod- ucts - see device summary) – Low voltage (LVD) reset ensuring proper power power-off of the device All ST7263 MCUs are available in ROM and OTP versions. The ST72E631 is the EPROM version of the ST7263 in CSDIP32 windowed packages. ...
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... ST7263 1.2 PIN DESCRIPTION Figure 2. 34-Pin SO Package Pinout PC2/USBOE AIN7/IT8/PB7 (10mA) AIN6/IT7/PB6 (10mA) AIN5/IT6/PB5 (10mA) AIN4/IT5/PB4 (10mA) AIN3/PB3 (10mA) AIN2/PB2 (10mA) AIN1/PB1 (10mA EPROM/OTP versions only PP Figure 3. 32-Pin SDIP Package Pinout PC2/USBOE AIN7/IT8/PB7 (10mA) AIN6/IT7/PB6 (10mA) V AIN5/IT6/PB5 (10mA) AIN4/IT5/PB4 (10mA) AIN3/PB3 (10mA) ...
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... 10mA 10mA 10mA ST7263 and V V DDA DD and . V V SSA SS Main Function Alternate Function (after reset) Power supply voltage (4V - 5.5V) Oscillator output Oscillator input Digital ground Port C2 USB Output Enable Port C1 SCI transmit data output Port C0 SCI Receive Data Input ...
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... ST7263 Pin n° Pin Name 20 21 PA5/ICAP2/IT2 I PA4/ICAP1/IT1 I PA3/EXTCLK I PA2/SCL I PA1/SDA I PA0/MCO I SSA 29 31 USBDP I USBDM I USBVCC DDA *: if the peripheral is present on the device (see Legend / Abbreviations for Figure 2 Type input output supply In/Output level CMOS 0.3V T Output level: 10mA = 10mA high sink (on N-buffer only) ...
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... An alternative solution is to program the unused ports as inputs with pull-up 0.1µF 10nF 4.7K 0.1µF RESET 0.1µF OSCIN See Clocks Section OSCOUT Or configure unused I/O ports by software as input with pull-up 10K V DD Unused I/O ST7263 9/109 ...
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... ST7263 1.4 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 192 bytes of register location 512 bytes of RAM and up to 16K bytes of user program memory. The RAM space includes bytes for the stack from 0100h to 013Fh ...
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... Timer Input Capture Low Register 2 Timer Output Compare High Register 2 Timer Output Compare Low Register 2 SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 ST7263 Reset Status Remarks 00h R/W 00h R/W 00h R/W ...
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... ST7263 Address Block Register Label 0025h PIDR 0026h DMAR 0027h IDR 0028h ISTR 0029h IMR 002Ah CTLR 002Bh USB DADDR 002Ch EP0RA 002Dh EP0RB 002Eh EP1RA 002Fh EP1RB 0030h EP2RA 0031h EP2RB 0032h 0038h 0039h 003Ah I OAR 003Bh 003Ch CCR 003Dh ...
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... An Ultraviolet source of wave length 2537 Å yield- ing a total integrated dosage of 15 Watt-sec/cm required to erase the ST72Exxx. The device will be erased minutes if such a UV lamp with a 12mW/cm from the device window without any interposed fil- ters. ST7263 power rating is placed 1 inch 13/109 in ...
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... ST7263 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer ...
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... No overflow or underflow has occurred overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions also affected by the “bit test and branch”, shift and rotate instructions. ST7263 th 15/109 ...
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... ST7263 CPU REGISTERS (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 3Fh SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is ...
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... Figure 9. Crystal/Ceramic Resonator . osc is recommended lists the rec- Figure 10. Clock block diagram 70 22pF 22pF 1- MHz Crystal specifications does (see Sec- OXOV OSCIN OSCOUT NC EXTERNAL CLOCK OSCOUT OSCIN OSCIN OSCOUT MHz CPU and peripherals) %3 CLKDIV 1 6 MHz (USB ST7263 17/109 ...
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... ST7263 3.2 RESET The Reset procedure is used to provide an orderly software start- exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external re- set at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point ...
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... Note: Refer to Electrical Characteristics for values of t Figure 12. Low Voltage Reset Signal Output RESET INTERNAL V DD RESET RESET Note: Hysteresis (V V IT+ temporization (4096 CPU clock cycles) $FFFE 4096 CPU CLOCK CYCLES DELAY , t DDR OXOV V IT IT+ IT- hys FFFF FFFE , and V IT+ IT- hys ST7263 V IT- 19/109 ...
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... ST7263 4 INTERRUPTS AND POWER SAVING MODES 4.1 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in Table 7 Interrupt Mapping maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled ...
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... FETCH NEXT INSTRUCTION N IRET Y RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT Register Description Label N/A ISTR ITRFRE TIMSR I2CSR1 I2CSR2 SCISR ISTR ST7263 N INTERRUPT Y STACK PC SET I BIT LOAD PC FROM INTERRUPT VECTOR Vector Exit Priority from Address Order HALT Highest yes FFFEh-FFFFh ...
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... ST7263 INTERRUPTS (Cont’d) 4.1.1 Interrupt Register INTERRUPTS REGISTER (ITRFRE) Address: 0008h — Read/Write Reset Value: 0000 0000 (00h) 7 IT8E IT7E IT6E IT5E IT4E Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits . 22/109 If an ITiE bit is set, the corresponding interrupt is generated when – ...
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... Figure 16. HALT Mode Flow Chart ). CPU N EXTERNAL INTERRUPT* Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the inter- rupt routine and cleared when the CC register is popped. ST7263 HALT INSTRUCTION OSCILLATOR OFF PERIPH. CLOCK OFF CPU CLOCK OFF I-BIT CLEARED ...
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... ST7263 POWER SAVING MODES (Cont’d) 4.2.3 WAIT mode WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced enable all interrupts ...
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... When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning : The alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. ST7263 25/109 ...
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... ST7263 I/O PORTS (Cont’d) Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multi- plexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input ...
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... IT3 Schmitt triggered input IT3E = 1 (ITIFRE) Timer OCMP2 push-pull IT4 Schmitt triggered input IT4E = 1 (ITIFRE) ALTERNATE ENABLE 1 0 ALTERNATE ENABLE 1 ALTERNATE ENABLE 0 CMOS SCHMITT TRIGGER ST7263 Alternate Function Condition MCO = 1 (MISCR) CC1 =1 CC0 = 1 (Timer CR2) IT1E = 1 (ITIFRE) OC1E = 1 OC2E = P-BUFFER V ...
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... ST7263 I/O PORTS (Cont’d) Table 10. PA1, PA2 Description PORT A Input* PA1 without pull-up PA2 without pull-up *Reset State Figure 19. PA1, PA2 Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL 28/109 Output Very High Current open drain SDA (I2C data) ...
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... ALTERNATE ENABLE DIGITAL ENABLE 0 Alternate Function Condition CH[2:0] = 000 (ADCCSR) CH[2:0] = 001 (ADCCSR) CH[2:0]= 010 (ADCCSR) CH[2:0]= 011 (ADCCSR) CH[2:0]= 100 (ADCCSR) CH[2:0]= 101 (ADCCSR) CH[2:0]= 110 (ADCCSR) CH[2:0]= 111 (ADCCSR P-BUFFER PAD ANALOG SWITCH DIODES N-BUFFER V SS ST7263 29/109 ...
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... ST7263 I/O PORTS (Cont’d) 5.1.6 Port C Table 12. Port C Description PORT C Input* PC0 with pull-up PC1 with pull-up PC2 with pull-up *Reset State Figure 21. Port C Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL ALTERNATE INPUT 30/109 Output push-pull RDI (SCI input) ...
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... DD7 DD6 Bit 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode ST7263 DD5 DD4 DD3 DD2 DD1 LSB LSB LSB LSB LSB LSB ...
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... ST7263 5.2 MISCELLANEOUS REGISTER Address: 0009h — Read/Write Reset Value: 1111 0000 (F0h LVD Bit 7:4 = Reserved Bit 3 = LVD Low Voltage Detector. This bit is set by software and only cleared by hard- ware after a reset. 0: LVD enabled 1: LVD disabled 32/109 Bit 2 = CLKDIV Clock Divider . ...
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... T6 bit be- comes cleared. Figure 22. Watchdog Block Diagram RESET WDGA f CPU 5.3.2 Main Features Programmable timer (64 increments of 49152 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero WATCHDOG CONTROL REGISTER (CR 7-BIT DOWNCOUNTER CLOCK DIVIDER 49152 T1 T0 ST7263 33/109 ...
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... ST7263 WATCHDOG TIMER (Cont’d) 5.3.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over ...
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... WATCHDOG TIMER (Cont’d) Table 15. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) WDGCR WDGA 0C Reset Value ST7263 35/109 0 1 ...
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... ST7263 5.4 16-BIT TIMER 5.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and PWM ). ...
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... TIMER INTERNAL BUS 16 16 OUTPUT COMPARE CIRCUIT (Status Register) SR OLVL2 IEDG1 OLVL1 OC1E OC2E OPM Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) ST7263 INPUT INPUT CAPTURE CAPTURE REGISTER REGISTER EDGE DETECT ...
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... ST7263 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte value Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically ...
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... TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running. FFFD FFFE FFFF 0000 0001 0002 0003 FFFC FFFD 0000 FFFC FFFD ST7263 0001 0000 39/109 ...
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... ST7263 16-BIT TIMER (Cont’d) 5.4.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition is detected by the ICAP i pin (see figure 5) ...
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... TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge. Note: A EDGE DETECT ICIE CIRCUIT1 IC1R Register ICF1 FF02 ST7263 (Control Register 1) CR1 IEDG1 (Status Register) SR ICF2 (Control Register 2) CR2 CC0 IEDG2 CC1 FF03 FF03 41/109 ...
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... ST7263 16-BIT TIMER (Cont’d) 5.4.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- ...
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... FOLVL i bits have no effect in either One-Pulse mode or PWM mode. /2, OCF i and CPU Figure 8). This / CPU 9). R register and the i OC1E CC1 OC2E (Control Register 2) CR2 (Control Register 1) CR1 OCIE FOLV2 FOLV1 OLVL2 OCF1 OCF2 (Status Register) SR CC0 Latch OLVL1 1 Latch ST7263 OCMP1 Pin OCMP2 Pin 43/109 ...
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... ST7263 16-BIT TIMER (Cont’d) Figure 30. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 31. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) ...
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... ICIE is set. 5. When One Pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedi- cated to One Pulse mode. ST7263 CPU PRESC ...
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... ST7263 16-BIT TIMER (Cont’d) Figure 32. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 33. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 ...
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... FFFCh R register value required for a specific tim CPU * Value = PRESC = Signal or pulse period (in seconds) = CPU clock frequency (in hertz) = Timer prescaler factor ( depend- ing on CC[1:0] bits, see Table EXT = Signal or pulse period (in seconds) = External timer clock frequency (in hertz) Figure ST7263 1) 11) 47/109 ...
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... ST7263 16-BIT TIMER (Cont’d) 5.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken interrupt with “ ...
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... A falling edge triggers the capture rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ST7263 49/109 ...
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... ST7263 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Com- pare mode, both OLV1 and OLV2 in PWM and one-pulse mode) ...
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... CHR register. 7 MSB OUTPUT COMPARE (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB ST7263 0 LSB 0 LSB 1 HIGH REGISTER 0 LSB 1 LOW ...
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... ST7263 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 LOW (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...
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... Reset Value OC2HR MSB 1E 1 Reset Value OC2LR MSB 1F 0 Reset Value OC2E OPM PWM CC1 OCIE TOIE FOLV2 FOLV1 OCF1 TOF ICF2 OCF2 ST7263 CC0 IEDG2 EXEDG OLVL2 IEDG1 OLVL1 LSB LSB - - - LSB LSB LSB LSB LSB LSB LSB LSB - - - LSB 0 ...
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... ST7263 5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 5.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 5.5.2 Main Features Full duplex, asynchronous communications NRZ standard format (Mark/Space) Independently programmable transmit and receive baud rates up to 250K baud ...
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... Received Shift Register WAKE UP UNIT ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR Transmitter Rate /PR /16 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 BAUD RATE GENERATOR (Data Register) DR CR1 WAKE RECEIVER RECEIVER CONTROL CLOCK NF FE Control BRR Receiver Rate Control ST7263 SR - 55/109 ...
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... ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains 4 dedicated regis- ters: – Two control registers (CR1 & CR2) – A status register (SR) – A baud rate register (BRR) Refer to the register descriptions in for the definitions of each bit ...
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... Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, i.e. before writing the next byte in the DR. ST7263 57/109 ...
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... ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg- ister. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin ...
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... The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to re- ceive this word normally and to use ad- dress word. ST7263 59/109 ...
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... ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 5.5.6 Interrupts Interrupt Event Transmit Data Register Empty ...
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... Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Reserved, forced by hardware to 0. ST7263 61/109 ...
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... ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1 ...
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... These 3 bits, in conjunction with the SCP1 & SCP0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. RR Dividing Factor 0 SCR2 SCR1 SCR0 SCP1 SCP0 SCT2 SCT1 128 1 1 SCR2 SCR1 128 1 1 ST7263 SCT0 SCR0 63/109 ...
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... ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 18. SCI Register Map and Reset Values Address Register (Hex.) Label 20 SR TDRE Reset Value 21 DR DR7 Reset Value 22 BRR SCP1 Reset Value 23 CR1 Reset Value 24 CR2 Reset Value 64/109 RDRF IDLE DR6 DR5 DR4 ...
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... DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, applica- tion software can know which USB event has oc- curred. 6 MHz ENDPOINT REGISTERS SIE DMA INTERRUPT REGISTERS ST7263 CPU Address, data buses and interrupts MEMORY 65/109 ...
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... ST7263 USB INTERFACE (Cont’d) 5.6.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined 7 DA15 DA14 DA13 DA12 DA11 Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6 ...
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... Bit 4 = ERR Error. This bit is set by hardware whenever one of the er- rors listed below has occurred error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected ST7263 CTR ERR IOVR ESUSP RESET 67/109 0 SOF ...
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... ST7263 USB INTERFACE (Cont’d) Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software overrun detected 1: Overrun detected Bit 2 = ESUSP End suspend mode . This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB in- terface up from suspend mode ...
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... Bits 3:0 = TBC[3:0] Transmit byte count for End- point n. Before transmission, after filling the transmit buff- er, software must write in the TBC field the trans- mit packet size expressed in bytes (in the range 0- 8). ST7263 USB host. DTOG_TX and DISABLED: transmission 0 transfers cannot be executed. ...
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... ST7263 USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh) 7 DTOG STAT STAT CTRL EA3 _RX _RX1 _RX0 These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. ...
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... Note: When a CTR interrupt occurs, the TP3- TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register. ST7263 endpoint number 71/109 ...
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... ST7263 USB INTERFACE (Cont’d) Table 19. USB Register Map and Reset Values Address Register 7 Name (Hex.) PIDR TP3 25 Reset Value x DMAR DA15 26 Reset Value x IDR DA7 27 Reset Value x ISTR SUSP 28 Reset Value 0 IMR SUSPM 29 Reset Value 0 CTLR 0 2A Reset Value 0 DADDR ...
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... MSB first. The first byte following the start condi- tion is the address byte always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to ure 1. MSB 1 2 ACK 8 9 STOP CONDITION ST7263 Fig- VR02119B 73/109 ...
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... ST7263 I²C BUS INTERFACE (Cont’d) The Acknowledge function may be enabled and disabled by software. The I²C interface address and/or general call ad- dress can be selected by software. The speed of the I²C interface may be selected be- tween Standard (0-100 kHz) and Fast I²C (100- 400 kHz). ...
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... How to Release the SDA / SCL lines Set and subsequently clear the STOP bit while Transfer sequenc- BTF is set. The SDA/SCL lines are released after the transfer of the current byte. Figure 3 Transfer sequencing Figure 3 Transfer sequencing EV4). ST7263 75/109 ...
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... ST7263 I²C BUS INTERFACE (Cont’d) 5.7.4.2 Master Mode To switch from default Slave mode to Master mode, a Start condition generation is needed. Start Condition and Transmit Slave Address Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condi- tion ...
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... EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. A Data2 A EV2 EV2 Data1 A Data2 A EV3 Data1 A Data2 A EV7 Data1 A Data2 EV8 DataN A P ..... EV2 EV4 DataN NA ..... EV3 EV3-1 DataN NA ..... EV7 EV7 A DataN A ..... EV8 ST7263 P EV4 P P EV8 77/109 ...
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... ST7263 I²C BUS INTERFACE (Cont’d) 5.7.5 Low Power Modes Mode Description No effect on I²C interface. WAIT I²C interrupts exit from Wait mode. I²C registers are frozen. In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C HALT interface resumes operation when the MCU is woken interrupt with “ ...
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... This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 4 events and the interrupt. SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See ST7263 for the relationship between the Figure 3) is detected. 79/109 ...
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... ST7263 I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event oc- curs cleared by software reading SR2 register in case of error event or as described in is also cleared by hardware when the interface is disabled (PE=0) ...
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... Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call ad- dress is detected on the bus while ENGC= cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0 general call address detected on bus 1: general call address detected on bus ST7263 81/109 ...
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... ST7263 I²C BUS INTERFACE (Cont’d) I²C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I²C mode. This bit is set and cleared by software not cleared when the interface is disabled (PE=0). ...
Page 83
... Table 20 Register Map Address Register 7 Name (Hex OAR 3C CCR FM/SM 3D SR2 3E SR1 EVF DR7 .. DR0 ADD7 .. ADD0 CC6 .. CC0 AF STOPF TRA BUSY BTF PE ENGC START ST7263 ARLO BERR GCAL ADSL M/SL SB ACK STOP ITE 83/109 ...
Page 84
... ST7263 5.8 8-BIT A/D CONVERTER (ADC) 5.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources ...
Page 85
... ADON bit. This feature allows reduced power consumption when no conversion is need- ed. Mode WAIT HALT 5.8.5 Interrupts None ST7263 Table 21 Selection. Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed. 85/109 ...
Page 86
... ST7263 8-BIT A/D CONVERTER (ADC) (Cont’d) 5.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO - ADON 0 - Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by soft- ware reading the result in the DR register or writing to the CSR register. ...
Page 87
... PC-128/PC+127 bset $10,#7 00..FF bset [$10],#7 00..FF btjt $10,#7,skip 00..FF btjt [$10],#7,skip 00..FF Pointer Pointer Length Address Size (Bytes) (Hex.) (Hex (with X register (with Y register 00..FF byte + 2 00..FF word + 2 00..FF byte + 2 00..FF word + 00..FF byte + 00..FF byte + 00..FF byte + 3 ST7263 87/109 ...
Page 88
... ST7263 ST7 ADDRESSING MODES (Cont’d) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For Interrupt (Low Power ...
Page 89
... The relative addressing mode consists of two sub- modes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the ad- dress follows the opcode. Indexed Function Function ST7263 Swap Nibbles Call or Jump subroutine Function Conditional Jump Call Relative 89/109 ...
Page 90
... ST7263 6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call ...
Page 91
... Jump JRNC Jump JRULT Jump JRUGE Jump JRUGT Jump Function/Example Dst tst ( bres Byte bset Byte btjf Byte, #3, Jmp1 M btjt Byte, #3, Jmp1 M reg, M tst(Reg - M) reg FFH-A reg, M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * Unsigned < Jmp if unsigned >= Unsigned > ST7263 Src 91/109 ...
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... ST7263 INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2’s compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry flag RET Subroutine Return RIM Enable Interrupts RLC ...
Page 93
... Exposure to maxi- mum rating conditions for extended periods may affect device reliability. Ratings / also recommended and together on application DDA DD and ). V V SSA Value - 0.3 to +6.0 - 0 80 -65 to +150 150 350 2000 ST7263 Unit °C °C ° 93/109 ...
Page 94
... ST7263 7.2 THERMAL CHARACTERISTICS The average chip-junction temperature, T grees Celsius, may be calculated using the follow- ing equation Where: – the Ambient Temperature – the Package Junction-to-Ambient Thermal A Resistance, in C/W, – the sum of P and P D INT I/O – the product of I INT DD and Watts ...
Page 95
... Note 1: USB 1.1 specifies that the power supply must be between 4.00 and 5.25 Volts. The USB cell is therefore guaranteed only in that range. Conditions MHz ; USB not guaranteed CPU MHz ; USB not guaranteed CPU MHz or 4 MHz CPU USB guaranteed MHz or 4 MHz CPU USB not guaranteed ST7263 Min Max Unit 3.00 4. 4.00 IT+ 4.0 5.25 V 5.25 5. ...
Page 96
... ST7263 7.4 POWER CONSUMPTION ( +70°C unless otherwise specified) A GENERAL Symbol Parameter V Operating Supply Voltage DD V Analog Reference Voltage DDA CPU RUN mode (see Note 1) CPU WAIT mode (See Note CPU HALT mode (see Note 3) USB Suspend mode (see Note 4) Note 1: All peripherals running. ...
Page 97
... All voltages are referred to V unless otherwise specified SS Note 1: Guaranteed by design, not tested in production. Note 2: Data based on characterization results, not tested in production. Conditions I = -25mA V = -1.6mA V = -10mA V = 1.6mA 10mA OH Leading Edge Trailing Edge CL=50pF Between 10% and 90 ST7263 Min Typ Max Unit - - 0.7xV 0.3xV V ...
Page 98
... ST7263 7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS LOW VOLTAGE RESET Electrical Specifications Symbol Parameter Low Voltage Reset Threshold V IT+ V rising DD Low Voltage Reset Threshold V IT- V falling DD V Hysteresis (V hys IT+ 7.7 CONTROL TIMING CHARACTERISTICS (Operating conditions +70°C unless otherwise specified) A CONTROL TIMINGS ...
Page 99
... DD Symbol Conditions VDI I(D+, D-) VCM Includes VDI range VSE VOL RL of 1.5K ohms to 3.6v VOH RL of 15K ohm to V USBV V =5v DD Min. Max. 0.2 0.8 2.5 0.8 2.0 0.3 2.8 3.6 SS 3.00 3.60 ST7263 Unit 99/109 ...
Page 100
... ST7263 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 44. USB: Data signal Rise and fall time Differential Data Lines VCRS USB: Low speed electrical characteristics Parameter Driver characteristics: Rise time Fall Time Rise/ Fall Time matching Output signal Crossover Voltage Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Elec- trical) of the USB specification (version 1 ...
Page 101
... Min Max Min 4.7 1.3 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 (1) 0 (1) 250 100 1000 20+0.1Cb 300 20+0.1Cb 4.0 0.6 400 ST7263 Symbol Unit Max T ms BUF T s HD:STA T s LOW T s HIGH T s SU:STA 0.9( HD:DAT T ns ...
Page 102
... ST7263 7.9 8-BIT ADC CHARACTERISTICS Digital Result ADCDR 255 V – V 254 DDA SSA 1LSB = ---------------------------------------- - i deal 256 253 B(ideal ADC Analog to Digital Converter (8-bit) Symbol Parameter |TUE| Total unadjusted error* OE Offset error* GE Gain Error* |DLE| Differential linearity error* |ILE| Integral linearity error* ...
Page 103
... ADC CHARACTERISTICS (Cont’d) R AIN V AIN Px.x/AINx C = input capacitance pin V = threshold voltage sampling switch C = sample/hold hold capacitance leakage = leakage current at the pin due to various junctions 0. pin 5pF V = 0.6V T ST7263 Sampling Switch SS C 22.4 pF leakage ±1µA V hold SS 103/109 ...
Page 104
... ST7263 8 PACKAGE CHARACTERISTICS 8.1 PACKAGE MECHANICAL DATA Figure 45. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width 0.10mm .004 seating plane Figure 46. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width See Lead Detail 104/109 SO34S VR01725J N/2 mm inches Dim. Min Typ Max ...
Page 105
... D1 26.67 E 10. 14. Ø CDIP32SW N ST7263 mm inches Typ Max Min Typ Max 3.63 0.143 0.015 0.46 0.58 0.014 0.018 0.023 0.89 1.14 0.025 0.035 0.045 0.25 0.36 0.008 0.010 0.014 1.050 0.400 9.91 10.36 0.372 0.390 0.408 1 ...
Page 106
... ROM Code (three letters Plastic DIP M = Plastic SO Note 1. /xxx stands for the ROM code name as- signed by STMicroelectronics. RAM Package (bytes) Table 27. Development Tools CSDIP32 Development Tool SO34 Real time emulator ST7263-EMU2 512 EPROM PSDIP32 Programming Board SO34 256 PSDIP32 SO34 256 PSDIP32 ...
Page 107
... ST7263X MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference : . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references: Device: Package: Special Marking: For marking, one line is possible with maximum 13 characters. Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. We have checked the ROM code verification file returned STMicroelectronics. It conforms exactly with the ROM code file orginally supplied ...
Page 108
... BRUSHLESS DC MOTOR DRIVE WITH ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1182 USING THE ST7 USB LOW-SPEED FIRMWARE PRODUCT OPTIMIZATION AN982 USING CERAMIC RESONATORS WITH THE ST7 ...
Page 109
... Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Main changes section 9.3 on page 108. 2001 STMicroelectronics - All Rights Reserved Standard Specification as defined by Philips. STMicroelectronics Group of Companies Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com ST7263 Date August Patent. Rights to use these components in an 109/109 ...