ST7263BK2 STMicroelectronics, ST7263BK2 Datasheet - Page 61

• Manufacturer Part Number: ST7263BK2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
Note:
Figure 28. 16-bit read sequence (from either the Counter register or the Alternate
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
●
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1.
2.
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
The TOF bit of the SR register is set.
A timer interrupt is generated if:
–
–
Reading the SR register while the TOF bit is set.
An access (read or write) to the CLR register.
TOIE bit of the CR1 register is set and
I bit of the CC register is cleared.
Counter register)
At t0
At t0 +Δt
Beginning of the sequence
Sequence completed
Read
MS Byte
Read
LS Byte
Doc ID 7516 Rev 8
instructions
Other
Returns the buffered
LS Byte value at t0
is buffered
LS Byte
On-chip peripherals
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