ST72324BK6-Auto STMicroelectronics, ST72324BK6-Auto Datasheet - Page 97

• Manufacturer Part Number: ST72324BK6-Auto
• Description: 8-bit MCU for automotive, 3.8 to 5.5V operating range with 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST72324BK6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
• 4 Power Saving Modes: Slow, Wait, Active Halt, and Halt

ST72324B-Auto
Table 52.
10.4
10.4.1
10.4.2
Timer A: 35
Timer B: 45
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer A: 3E
Timer B: 4E
Timer A: 3F
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer A: 3C
Timer B: 4C
Timer A: 3D
Timer B: 4D
Address
(Hex.)
16-bit timer register map and reset values (continued)
Serial peripheral interface (SPI)
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface can not be a master in a multi-master system.
Main features
●
●
●
●
●
●
●
●
●
IC1LR
Reset value
OC1HR
Reset value
OC1LR
Reset value
OC2HR
Reset value
OC2LR
Reset value
CHR
Reset value
CLR
Reset value
ACHR
Reset value
ACLR
Reset value
IC2HR
Reset value
IC2LR
Reset value
Register
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master mode fault and Overrun flags
CPU
label
/2 max. slave mode frequency (see note)
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
7
x
1
0
1
0
1
1
1
1
x
x
6
x
0
0
0
0
1
1
1
1
x
x
Doc ID13466 Rev 4
CPU
/4 max.)
5
0
0
0
0
1
1
1
1
x
x
x
4
0
0
0
0
1
1
1
1
x
x
x
3
x
0
0
0
0
1
1
1
1
x
x
2
x
0
0
0
0
1
1
1
1
x
x
On-chip peripherals
1
x
0
0
0
0
1
0
1
0
x
x
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
97/198
0
0
0
0
0
1
0
1
0
x
x
x