ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 44

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
44/265
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
N
WATCHDOG
WDGHALT
(MCCSR.OIE=0)
RESET
1
INTERRUPT
Y
1)
3)
ENABLE
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
I[1:0] BITS
AWU RC OSC
I[1:0] BITS
N
CYCLE
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
4)
4)
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to
Mapping,” on page 34
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
for more details.
Table 9, “Interrupt