ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 57

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

WINDOW WATCHDOG (Cont’d)
Figure 37. Window Watchdog Timing Diagram
10.1.6 Low Power Modes
10.1.7 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
ACTIVE
HALT
SLOW
Mode
HALT
WAIT
Description
No effect on Watchdog: The downcounter continues to decrement at normal speed.
No effect on Watchdog: The downcounter continues to decrement.
OIE bit in
MCCSR
register
0
0
1
WDGWR
3Fh
T6 bit
Reset
T[5:0] CNT downcounter
WDGHALT bit
in Option
Byte
0
1
x
Refresh not allowed
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
Refresh Window
10.1.8 Using Halt Mode with the WDG
(WDGHALT option)
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
(step = 16384/f
Section 0.1.8
time
below.
OSC2
)
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