ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 64

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321Rx ST72321ARx ST72321Jx
ON-CHIP PERIPHERALS (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ARTICRx registers.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ARTICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ARTICCSR register.
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
Note: During HALT mode, if both input capture
and external clock are enabled, the ARTICRx reg-
ister value is not guaranteed if the input capture
pin and the external clock change simultaneously.
Figure 41. Input Capture Timing Diagram
64/193
ICRx REGISTER
ARTICx PIN
COUNTER
CFx FLAG
COUNTER
f
COUNTER
).
01h
02h
xxh
03h
04h
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. After fetching the
interrupt vector, the CFx flags can be read to iden-
tify the interrupt source.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
05h
INTERRUPT
04h
06h
07h
t