ST10F276Z5 STMicroelectronics, ST10F276Z5 Datasheet - Page 226

no-image

ST10F276Z5

Manufacturer Part Number
ST10F276Z5
Description
16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10F276Z5

Single Voltage Supply
5V ±10% (embedded regulator for 1.8 V core supply)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F276Z5Q3
Manufacturer:
AD
Quantity:
230
Part Number:
ST10F276Z5Q3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F276Z5Q3TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F276Z5T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F276Z5T3
Manufacturer:
ST
0
Company:
Part Number:
ST10F276Z5T3
Quantity:
9 000
Electrical characteristics
226/239
Slave mode
V
Table 111. Slave mode
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
2. Formula for SSC Clock Cycle time:
t
t
t
t
t
t
t
t
t
t
t
310
311
312
313
314
315
316
317p
318p
317
318
Symbol
DD
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baud rate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after checking that timings
are in line with the target master).
t
Where <SSCBR> represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
310
= 5 V ±10%, V
SR
SR
SR
SR
SR
CC
CC
SR
SR
SR
SR
= 4 TCL * (<SSCBR> + 1)
SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift
edge
Write data hold after shift
edge
Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
Read data hold time after
latch edge, phase error
detection on (SSCPEN = 1)
Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
Read data hold time after
latch edge, phase error
detection off (SSCPEN = 0)
Parameter
SS
= 0 V, T
310
is 125ns (corresponding to 8Mbaud).
A
(2)
= -40 to +125 °C, C
(<SSCBR> = 0002h)
@F
Min.
Max. baud rate
150
63
62
87
31
0
6
6.6 MBd
CPU
= 40 MHz
(1)
Max.
L
150
10
55
= 50 pF
t
310
4TCL + 12
6TCL + 12
2TCL + 6
(<SSCBR> = 0001h -
8TCL
Variable baud rate
Min.
/ 2 – 12
0
6
FFFFh)
262144 TCL
2TCL + 30
Max.
10
ST10F276Z5
Unit
ns

Related parts for ST10F276Z5