L6615 STMicroelectronics, L6615 Datasheet - Page 10

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L6615

Manufacturer Part Number
L6615
Description
High/low side load share controller
Manufacturer
STMicroelectronics
Datasheet

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L6615
3
The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so, for the master
power supply, V
In the slave converters, being V
diagram) isolates the output this amplifier from the share bus.
The Share Sense Amplifier (SSA) reads the bus voltage transferring the signal to the non-inverting input
of the error amplifier where it is compared with CGA voltage.
Whenever a controller acts as the master in the system, the voltage difference between the E/A inputs is
zero. To guarantee its output low in such condition, a 40mV offset is inserted in series with the inverting
input.
Instead in the slave converters the input voltage difference is proportional to the difference between the
master load current and the relevant slave load current.
The transconductance E/A converts the V at its inputs in a current equal to
flowing in the compensation network connected between COMP pin and ground.
The E/A output voltage drives the adjust amplifier to sink current from the ADJ pin that is connected to the
output voltage through a small resistor along the sense path. The current sunk by ADJ pin is deviated from
feedback path of the slave power supply that reacts increasing its duty cycle.
In steady state the current sunk by the ADJ pin is proportional to the value of error amplifier output.
4
The first design step is usually the choice of the sense resistor whose maximum value is limited by power
dissipation; this constraint must be traded off against the precision of L6615 current sensing. In fact a small
sense resistance value lowers the power dissipation but reduces the signal available at the inputs of the
L6615 current sense amplifier.
Once fixed R
specs: usually these specs define the share bus voltage (V
supplies.
Their value must comply with the constraints imposed by the L6615:
Figure 11. Simplified feedback block diagram.
10/20
V
V
SHARE DRIVE SECTION, ERROR AMPLIFIER AND ADJUST AMPLIFIER
DESIGNING WITH L6615
REF
REF
CONTROLLER
CONTROLLER
+
+
STAGE 1
STAGE 1
POWER
POWER
K*V
K*V
PWM
PWM
SENSE
OUT
OUT
CGA
-
-
+
+
(*)
(*)
then the values for R
= V
SH
G
G
M
M
*Z
*Z
; the voltage on the share bus is imposed by the master.
COMP
COMP
R
R
A
A
(s)*R
(s)*R
* R
* R
R
R
CGA(SLAVE)
I
I
SENSE
SENSE
OUT(1)
OUT(1)
CGA
CGA
ADJ
ADJ
/ R
/ R
-
-
G
G
feedback divider ratio
feedback divider ratio
(*) K depends on the
(*) K depends on the
G
and R
< V
+
+
I
O UT
SHARE BUS
SHARE BUS
CGA(MASTER)
GCA
V
V
=
Z
Z
OUT
OUT
L
L
G
M
will be chosen in accordance with the application
I
I
LOAD
LOAD
V
+
+
SH(MAX)
, the diode at the output of SDA (see block
R
R
* R
* R
-
-
I
I
) and the number of paralleled power
OUT(2)
OUT(2)
SENSE
SENSE
G
G
CGA
CGA
M
M
*Z
*Z
/ R
/ R
COMP
COMP
G
G
R
R
(s)*R
(s)*R
A
A
ADJ
ADJ
CONTROLLER
CONTROLLER
STAGE 2
STAGE 2
POWER
POWER
+
+
K*V
K*V
-
-
PWM
PWM
OUT
OUT
+
+
(*)
(*)
V
V
REF
REF

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