PM6681A STMicroelectronics, PM6681A Datasheet - Page 36

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PM6681A

Manufacturer Part Number
PM6681A
Description
Dual synchronous step down controller with adjustable LDO
Manufacturer
STMicroelectronics
Datasheet

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Design guidelines
36/47
Equation 27
Due to the capacitive divider (C
Equation 28
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.
If the ripple is very small (lower than approximately 30 mV), a further compensation network,
named virtual ESR network, is needed. This additional part generates a triangular ripple
that is added to the ESR output voltage ripple at the input of the integrator network. The
complete control schematic is represented in
Figure 40. Virtual ESR network
The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR R
A good trade-off is to design the network in order to achieve an R
Equation 29
ESR
.
V
RIPPLE
INT
=
R
INT
INT
V
, C
RIPPLEout
R
=
ESR
filt
2
), the ripple voltage at the COMP pin is given by:
π
=
×
×
V
f
CUT
RIPPLE
C
Figure 40
INT
I
L
×
C
1
C
INT
C
+
INT
INT
C
R
filt
out
×
+
.
C
=
C
filt
filt
V
RIPPLEout
ESR
×
q
given by:
PM6681A

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