DS1342 Maxim, DS1342 Datasheet - Page 12

• Manufacturer Part Number: DS1342
• Description: The DS1341/DS1342 low-current real-time clocks (RTCs) are timekeeping devices that provide an extremely low standby current, which permits longer life from a power supply
• Manufacturer: Maxim

Low-Current I
Bit 7: Oscillator Stop Flag (OSF). If the OSF bit is a 1,
that indicates the oscillator has stopped or was stopped
for some period of time, and could be used to judge
the validity of the clock and calendar data. This bit is
edge triggered and is set to 1 when the internal circuitry
senses the oscillator has transitioned from a normal run
state to a STOP condition. The following are examples of
conditions that can cause the OSF bit to be set:
1) Power is applied for the first time.
2) The voltage present on V
3) The EOSC bit is turned off.
4) There are external influences on the crystal (e.g.,
This bit remains at 1 until written to 0. Attempting to write
OSF to 1 leaves the value unchanged.
Bit 6: Disable Oscillator Stop Flag (DOSF). This bit,
when set to 1, disables the sensing of the oscillator
conditions that would set the OSF bit. OSF remains
at 0 regardless of what happens to the oscillator.
This bit is cleared (0) when power is first applied.
Disabling the oscillator sensing is useful in reducing
power consumption.
Bit 5: Loss of Signal (LOS). This status bit indicates the
state of the CLKIN pin. The bit is set to 1 when the RTC
counter is no longer conditioned by the external clock.
This happens when ECLK = 0, or when the clock signal
at CLKIN stops toggling, or when the CLKIN frequency
differs more than Q0.8% from the selected input fre-
quency. This bit remains at 1 until written to 0. Attempting
to write LOS to 1 leaves the value unchanged. Clearing
the LOS flag when the CLKIN frequency is invalid inhibits
subsequent detections of the input frequency deviation.
Bits 4 and 3: Select Clock Source (CLKSEL[2:1]).
These two register bits select the clock source to drive
the RTC counter. Table 6 lists the input frequencies that
can be selected. Upon power-up, the bits are cleared to
0 and the 1Hz rate is selected.
12
oscillation.
noise, leakage, etc.).
BIT 7
OSF
1
Control/Status Register (0Fh)
DOSF
BIT 6
0
CC
is insufficient to support
2
BIT 5
LOS
C RTCs for High-ESR Crystals
1
CLKSEL2
BIT 4
0
Table 6. Input Frequency Options
Bit 2: Enable External Clock Input (ECLK). This bit
controls the direction of the CLKIN/INTA pin (see Table
5). When the ECLK bit is 1, the CLKIN/INTA pin is an
input, with the expected input rate defined by the state
of CLKSEL2 and CLKSEL1 (see Table 6).
When the ECLK bit is 0, the CLKIN/INTA pin is an
interrupt output (see Table 5). If the INTCN bit is 0,
CLKIN/INTA contains the status of A1F (provided that
the A1IE bit is 1) or A2F (provided that the A2IE bit is 1).
If the INTCN bit is 1, CLKIN/INTA contains the status of
A1F (provided that the A1IE bit is 1).
This bit is set to 0 when power is first applied.
Bit 1: Alarm 2 Flag (A2F). A 1 in the alarm 2 flag bit
indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either
CLKIN/INTA or SQW/INTB depending on the status of
the INTCN bit in the Control register. If the INTCN bit is
set to 0 and A2F bit is a 1 (and A2IE bit is also 1), the
CLKIN/INTA pin goes low. If the INTCN bit is set to 1 and
A2F bit is 1 (and A2IE bit is also 1), the SQW/INTB pin
goes low. The A2F bit is cleared when written to 0. This
bit can only be written to 0. Attempting to write this bit to
1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A 1 in the alarm 1 flag bit
indicates that the time matched the alarm 1 registers. If
the A1IE bit is also 1, the CLKIN/INTA pin goes low. A1F
is cleared when written to 0. This bit can only be written
to 0. Attempting to write this bit to 1 leaves the value
unchanged.
CLKSEL1
BIT 3
0
CLKSEL2
0
0
1
1
Control/Status Register Bitmap (0Fh)
ECLK
BIT 2
0
CLKSEL1
0
1
0
1
BIT 1
A2F
X
32.768kHz Input
CLKIN/INTA
50Hz Input
60Hz Input
1Hz Input
BIT 0
A1F
X