DS1342 Maxim, DS1342 Datasheet - Page 9

• Manufacturer Part Number: DS1342
• Description: The DS1341/DS1342 low-current real-time clocks (RTCs) are timekeeping devices that provide an extremely low standby current, which permits longer life from a power supply
• Manufacturer: Maxim

the ECLK bit is set. The external clock reference must be
within the defined frequency tolerance prior to initializing
the LOS flag.
Table 1 shows the map for the DS1341/DS1342 regis-
ters. During a multibyte access, if the address pointer
reaches the end of the register space (0Fh), it wraps
around to location 00h. On either an I
address pointer incrementing to location 00h, the current
time is transferred to a second set of registers. The time
information is read from these secondary registers while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read.
Table 1. Register Map
Note: Bits listed as 0 always read back as 0 and cannot be written to a 1.
ADDRESS
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
Low-Current I
EOSC
CENT
A1M1
A1M2
A1M3
A1M4
A2M2
A2M3
A2M4
BIT 7
OSF
0
0
0
0
0
DY/DT
DY/DT
DOSF
BIT 6
12/24
12/24
12/24
0
0
0
0
10 Year
10 Seconds
10 Seconds
10 Minutes
10 Minutes
10 Minutes
AM/PM
AM/PM
AM/PM
EGFIL
BIT 5
10hr
10hr
10hr
LOS
0
0
10 Date
10 Date
10 Date
Register Map
CLKSEL2 CLKSEL1
10 MO
2
2
BIT 4
10hr
10hr
10hr
RS2
C START or
0
C RTCs for High-ESR Crystals
BIT 3
RS1
0
INTCN
ECLK
BIT 2
The I
between 1.8V and 5.5V and the EOSC bit is 0. The I
interface is accessible whenever V
To prevent invalid device operation, the I
should not be accessed when V
If a microcontroller connected to the DS1341/DS1342
resets during I
microcontroller and the DS1341/DS1342 could become
unsynchronized. When the microcontroller resets, the
DS1341/DS1342 I
known state by holding SCL low for t
limits the minimum frequency at which the I
can be operated. If data is being written to the device
Seconds
Seconds
Minutes
Minutes
Minutes
Month
Hour
Hour
Hour
Date
Year
Day,
Date
Day,
Date
2
C interface is guaranteed to operate when V
BIT 1
A2IE
Day
A2F
2
C communications, it is possible that the
BIT 0
A1IE
A1F
2
C interface can be placed into a
Alarm 1 Date
Alarm 2 Date
Alarm 1 Day,
Alarm 2 Day,
FUNCTION
Seconds
Seconds
Minutes
Century
Alarm 1
Alarm 1
Minutes
Alarm 1
Alarm 2
Minutes
Alarm 2
Control/
Control
Month/
Status
Hours
Hours
Hours
Date
Year
Day
CC
CC
is below +1.8V.
TIMEOUT
is at a valid level.
I
01–12 + Century
2
1–12 + AM/PM
1–12 + AM/PM
1–12+AM/PM
C Interface
2
RANGE
2
00–59
00–59
00–23
01–31
00–99
00–59
00–59
00–23
00–59
00–23
C interface
C interface
1–31
1–31
1–7
1–7
1–7
. Doing so
—
—
CC
2
is
C
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