DS80C390 Maxim, DS80C390 Datasheet - Page 45

• Manufacturer Part Number: DS80C390
• Description: The DS80C390 is a fast 8051-compatible microprocessor with dual CAN 2
• Manufacturer: Maxim

Table 13. Interrupt Summary
Unless marked, all flags must be cleared by the application software.
*Cleared automatically by hardware when the service routine is entered.
**If edge-triggered, flag is cleared automatically by hardware when the service routine is entered. If level-triggered, flag follows the state of the
CONTROLLER AREA NETWORK (CAN) MODULE
The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0B specification. CAN is a
highly robust, high-performance communication protocol for serial communications. Popular in a wide range of
applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows
for the construction of sophisticated networks with a minimum of external hardware.
The CAN controllers support the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15
messages, with the standard 8-byte data field, in each message. Fourteen of the 15 message centers are
programmable in either transmit or receive modes, with the 15th designated as a FIFO-buffered, receive-only
message center to help prevent data overruns. All message centers support two separate 8-bit media masks and
media arbitration fields for incoming message verification. This feature supports the use of higher-level protocols,
which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming
messages. Each message center can also be programmed independently to test incoming data with or without the
use of the global masks.
Global controls and status registers in each CAN unit allow the microcontroller to evaluate error messages,
generate interrupts, locate and validate new data, establish the CAN bus timing, establish identification mask bits,
and verify the source of individual messages. Each message center is individually equipped with the necessary
status and control bits to establish direction, identification mode (standard or extended), data field size, data status,
automatic remote frame request and acknowledgment, and perform masked or non-masked identification
acceptance testing.
CANBUS
SCON0
SCON1
NAME
WDTI
INT0
INT1
INT2
INT3
INT4
INT5
TF0
TF1
TF2
PFI
C0I
C1I
interrupt pin.
TI0 or RI0 from Serial Port 0
TI1 or RI1 from Serial Port 1
CAN0/1 Bus Activity
Power-Fail Interrupt
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Timer
DESCRIPTION
CAN0 Interrupt
CAN1 Interrupt
Timer 0
Timer 1
Timer 2
VECTOR
0Bh
1Bh
2Bh
3Bh
4Bh
5Bh
6Bh
7Bh
33h
03h
13h
23h
43h
53h
73h
63h
NATURAL
PRIORITY
45 of 53
10
11
12
13
15
14
0
1
2
3
4
5
6
7
8
9
WDIF (WDCON.3)
RI_0 (SCON0.0);
RI_1 (SCON1.0);
PFI (WDCON.4)
TI_0 (SCON0.1)
TI_1 (SCON1.1)
IE0 (TCON.1)**
IE1 (TCON.3)**
TF2 (T2CON.7)
TF0 (TCON.5)*
TF1 (TCON.7)*
IE2 (EXIF.4)
IE3 (EXIF.5)
IE4 (EXIF.6)
IE5 (EXIF.7)
FLAG BIT
various
various
various
EPFI (WDCON.5)
CANBIE (EIE.7)
ENABLE BIT
EWDI (EIE.4)
C0IE (EIE.6)
C1IE (EIE.5)
EX2 (EIE.0)
EX3 (EIE.1)
EX4 (EIE.2)
EX5 (EIE.3)
EX0 (IE.0)
EX1 (IE.2)
ES0 (IE.4)
ES1 (IE.6)
ET0 (IE.1)
ET1 (IE.3)
ET2 (IE.5)
CANBIP (EIP.7)
CONTROL BIT
PWDI (EIP.4)
C0IP (EIP.6)
C1IP (EIP.5)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
PRIORITY
PX0 (IP.0)
PX1 (IP.2)
PS0 (IP.4)
PS1 (IP.6)
PT0 (IP.1)
PT1 (IP.3)
PT2 (IP.7)
N/A