DS80C400 Maxim, DS80C400 Datasheet - Page 30

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

PIN
59
58
57
20
21
22
23
24
25
26
27
48
47
46
45
44
43
42
41
35
34
33
32
31
30
29
28
56
55
54
53
52
NAME
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
A13
A14
A15
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Port 3, I/O. Port 3 functions as an 8-bit, bidirectional I/O port, and as an alternate interface for several resources
found on the traditional 8051. The reset condition of Port 3 is all bits at logic 1 through a weak pullup. The logic
1 state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 4, I/O. Port 4 is composed of eight pins that are user programmable as I/O, extended program memory
chip enables, or extended address lines. The configuration of the eight pins is established through the
programming of the port 4 control register (P4CNT). Following a reset, and if EA is low, P4.3 to P4.1 are driven
high and are assigned as chip enables. Port pins P4.7 to P4.4 and P4.0 are cleared to low state and are
assigned as addresses and chip enable, respectively. Additional information on external memory interfacing is
found in the port 4 control register SFR description and other sections in the High-Speed Microcontroller User’s
Guide: Network Microcontroller Supplement.
Port
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Port 5, I/O. Port 5 can function as an 8-bit, bidirectional I/O port, the CAN interface, Timer 3 input, and/or as
peripheral-enable signals. The reset condition of Port 5 is all bits at logic 1 through a weak pullup. The logic 1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
Port 6, I/O. Port 6 can function as an 8-bit, bidirectional I/O port, as program and data memory address/chip-
enable signals, and/or a third serial port. The reset condition of Port 6 is all bits at logic 1 through a weak pullup.
The logic 1 state also serves as an input mode, since external circuits writing to the port can override the weak
pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until
either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong
transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port
once again becomes the output (and input) high state.
Port
P6.0
A10 Program/Data Memory Address 10
A11 Program/Data Memory Address 11
A12 Program/Data Memory Address 12
A13 Program/Data Memory Address 13
A14 Program/Data Memory Address 14
A15 Program/Data Memory Address 15
Alternate Function
RXD0 Serial Port 0 Receive
TXD0 Serial Port 0 Transmit
INT0 External Interrupt 0
INT1 External Interrupt 1
T0 Timer 0 External Input
T1/CLKO Timer 1 External Input/External Clock Output
WR External Data Memory Write Strobe
RD External Data Memory Read Strobe
Alternate Function
CE0 Program Memory Chip Enable 0
CE1 Program Memory Chip Enable 1
CE2 Program Memory Chip Enable 2
CE3 Program Memory Chip Enable 3
A16 Program/Data Memory Address 16
A17 Program/Data Memory Address 17
A18 Program/Data Memory Address 18
A19 Program/Data Memory Address 19
Alternate Function
C0TX CAN0 Transmit Output
C0RX CAN0 Receive Input
T3 Timer 3 External Input
None
PCE0 Peripheral Chip Enable 0
PCE1 Peripheral Chip Enable 1
PCE2 Peripheral Chip Enable 2
PCE3 Peripheral Chip Enable 3
Alternate Function
CE4 Program Memory Chip Enable 4
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FUNCTION