MAX7304 Maxim, MAX7304 Datasheet - Page 10

• Manufacturer Part Number: MAX7304
• Description: The MAX7304 consists of 16 port GPIOs, with 12 push-pull GPIOs and four open-drain GPIOs configurable as PWM-controlled LED drivers
• Manufacturer: Maxim

The GPIO values 1 and 2 registers contain the debounced
input data for all the GPIOs for PORT7–PORT0 and
PORT15–PORT8, respectively (see
in the
period delay prior to detecting a transition on the input
port. This prevents a false interrupt from occurring when
changing a port from an output to an input. The GPIO
values 1 and 2 registers reports the state of all input ports
regardless of any interrupt mask settings.
When writing to the GPIO values 1 and 2 registers, the
corresponding PORT_ voltage is set high when written 1
or cleared when written 0. Reading the port when config-
ured as an output always returns the value 0 for the cor-
responding port regardless of the output value.
Enabling bit D_ in this register enables the direct
level shifter between GPIO pins PORT15–PORT8 and
PORT7–PORT0 (see
tion). The level-shifting pairs are PORT0/PORT8, PORT1/
PORT9, etc. The direction of the level shifter is con-
trolled by the GPIO direction 2 register (0x35). When the
corresponding bit in the GPIO direction 2 register is set
to 0, PORT15–PORT8 are inputs, while PORT7–PORT0
are outputs. When the bit is set to 1, PORT7–PORT0 are
inputs, while PORT15–PORT8 are outputs.
The GPIO global configuration register controls the main
settings for the GPIO ports (see
Tables
Bit D5 enables interrupt generation for I
is the main enable/shutdown bit for the GPIOs. Bit D3
functions as a software reset for the GPIO registers
(0x31 to 0x5B). Bits D[2:0] set the fade-in/out time for the
GPIOs configured as constant-current sinks.
The GPIO debounce configuration register sets the
amount of time a GPIO must be held in order for the
device to register a logic transition (see
the
possible debounce times from 9ms up to 40ms.
The LED constant-current setting register sets the global
constant-current level (see
Tables
between 10mA and 20mA. This setting only applies to the
LED driver enabled pins, PORT15–PORT12.
Register Tables
Register Tables
section).
section). Bit D0 selects the global current values
GPIO Debounce Configuration Register (0x42)
LED Constant-Current Setting Register (0x43)
GPIO Values 1 and 2 Registers (0x3A, 0x3B)
GPIO Global Configuration Register (0x40)
GPIO Level-Shifter Enable Register (0x3C)
with High Level of Integrated ESD Protection
 Maxim Integrated Products 10
Table 15
section). Five bits (D[4:0]) set 32
section). There is one debounce
Level-Translating GPIO and LED Driver
Table 18
in the
Table 16
Register Tables
Tables 13
2
in the
C timeouts. D4
in the
Table 17
Register
Register
and
sec-
14
in
The common PWM ratio register stores the common con-
stant-current output PWM duty cycle (see
Register Tables
translate over to a PWM ratio in the same manner as the
individual PWM ratio registers (0x50 to 0x53). Ports can use
their own individual PWM value or the common PWM value.
Write to this register to change the PWM ratio of several
ports at once.
The I
which indicates if an I
20
clear an I
Each LED driver port has an individual PWM ratio reg-
ister, 0x50 to 0x53 (see
section). Use values 0x00 to 0xFE in these registers to
configure the number of cycles out of 256 the output
sinks current (LED is on), from 0 cycles to 254 cycles.
Use 0xFF to have an output continuously sink current
(always on). For applications requiring multiple ports
to have the same intensity, program a particular port’s
configuration register (0x54 to 0x57) to use the common
PWM ratio register (0x45). New PWM settings take place
at the beginning of a PWM cycle, to allow changes from
common intensity to individual intensity with no interrup-
tion in the PWM cycle.
Registers 0x54 to 0x57 set individual configurations for
each port (see
D5 sets the port’s PWM setting to either the common or
individual PWM setting. Bits D[4:2] enable and set the
port’s individual blink period from 0 to 4096ms. Bits D1
and D0 set a port’s blink duty cycle.
The interrupt mask 1 and 2 registers control which ports
trigger an interrupt for PORT7–PORT0 and PORT15–
PORT8, respectively (see
Register Tables
interrupt. Set the bit to 1 to mask the interrupt.
If the port that has generated the interrupt is not masked,
the interrupt causes the INT signal to assert. A read of the
GPIO values 1 and 2 registers (0x3A, 0x3B) is required
to deassert the INT pin. Note that transitions that occur
while the INT signal is asserted, but before the read of
in the
I
2
2
C timeout flag register contains a single bit (D0),
C-Interfaced 16-Port,
Interrupt Mask 1 and 2 Registers (0x58, 0x59)
I
2
2
Register Tables
C timeout initiated interrupt.
C Timeout Flag Register (0x48) (Read Only)
PORT12–PORT15 Individual PWM Ratio
Table 22
section). The values stored in this register
section). Set the bit to 0 to enable the
PORT12–PORT15 LED Configuration
Common PWM Ratio Register (0x45)
2
C timeout has occurred (see
Table 21
in the
section). Read this register to
Tables 23
Registers (0x50 to 0x53)
Registers (0x54 to 0x57)
Register Tables
in the
MAX7304
Register Tables
and
Table 19
24
section).
in the
in the
Table