MAX7306 Maxim, MAX7306 Datasheet - Page 20

• Manufacturer Part Number: MAX7306
• Description: The MAX7306/MAX7307 I²C-/SMBus™-compatible, serial-interfaced peripherals feature four level-translating I/Os and operate from a 1
• Manufacturer: Maxim

SMBus/I
GPIOs and LED Drivers
same rules as for a write. Thus, a read is initiated by first
configuring the MAX7306/MAX7307’s command byte
by performing a write (Figure 13). The master can now
read n consecutive bytes from the MAX7306/
MAX7307 with the first data byte being read from the
register addressed by the initialized command byte
(Figure 15). When performing read-after-write verifica-
tion, remember to reset the command byte’s address
because the stored command byte address has been
autoincremented after the write (see Table 1).
If the MAX7306/MAX7307 are operated on a 2-wire
interface with multiple masters, a master reading the
MAX7306/MAX7307 should use a repeated start
between the write that sets the MAX7306/MAX7307’s
Figure 14. Write to Output Port Registers
Figure 15. Read from Input Port Registers
Figure 16. Interrupt and Reset Timing
20
P4–P1
P4–P1
P4–P1
SCL
SDA
SDA
SDA
INT
SCL
SCL
______________________________________________________________________________________
INTERRUPT VALID/RESET
(P4)
WRITE TO OUTPUT PORTS REGISTERS
START CONDITION
READ FROM INPUT PORTS REGISTERS
START CONDITION
START CONDITION
S
S
S
1
1
1
1
1
1
2
2
2
0
0
0
DATA1
SLAVE ADDRESS
3
3
3
0
0
0
2
4
DATA1
1
4
4
1
1
Operation with Multiple Masters
C Interfaced 4-Port, Level-Translating
5
1
5
5
1
1
6
A1
6
t
6
A1
1
IV
A0
7
A0
7
7
A0
R/W
R/W
8
0
R/W
8
8
1
1
t
PH
ACKNOWLEDGE FROM SLAVE
9
A
9
A
ACKNOWLEDGE FROM SLAVE
9
ACKNOWLEDGE FROM SLAVE
A
DATA2
MSB
0
MSB
0
DATA2
t
IR
0
REGISTER ADDRESS
0
DATA1
DATA2
0
t
IV
address pointer, and the read(s) that takes the data
from the location(s). This is because it is possible for
master 2 to take over the bus after master 1 has set up
the MAX7306/MAX7307’s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes the MAX7306/MAX7307’s address pointer,
then master 1’s delayed read can be from an unexpect-
ed location.
Clear device configuration register 0x27 bit D7 to
enable the bus timeout function (see Table 2), or set it
to disable the bus timeout function. Enabling the time-
out feature resets the MAX7306/MAX7307 serial-bus
interface when SCL stops either high or low during a
read or write. If either SCL or SDA is low for more than
1
DATA3
0
0
t
PSU
LSB
LSB
ACKNOWLEDGE FROM SLAVE
A
A
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
A
MSB
MSB
MSB
DATA3
t
IR
DATA
DATA4
DATA4
DATA3
LSB
Bus Timeout
ACKNOWLEDGE
LSB
t
PPV
LSB
NO ACKNOWLEDGE
A
A
NO ACKNOWLEDGE
NA
DATA VALID
NA
STOP
P
STOP
P
STOP
P